82371FB Datasheet, PDF (118/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
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5.0. TESTABILITY (PIIX/PIIX3)
5.1. Test Mode Description
The test modes are decoded from the IRQ inputs (IRQ 7, 6, 5) and qualified with the TESTIN# pin. Test mode
selection is asynchronous. These signals need to remain in their respective state for the duration of the test
modes. The test modes are defined as follows.
Table 17. Test Modes
Test Mode
IRQ7
IRQ6
IRQ5
TESTIN#
NAND Tree
0
x
x
0
NAND Tree
x
x
0
0
Tri-state All Outputs
1
1
1
0
5.2. NAND Tree Mode
Tri-states all outputs and bi-directional buffers except for XDIR and DACK1#. Every output buffer except for
XDIR and DACK1# is configured as an input in NAND tree mode and included in the NAND chain. The first
input of the NAND chain is MDRQ1, and the NAND chain is routed counter-clockwise around the chip (e.g.,
MDRQ1, MDRQ0, MDAK1#, . . .). DACK1# is an intermediate output, and XDIR is the final output. PCICLK
and TESTIN# are the only input pins not included in the NAND chain. Note in the table above there are two
possible ways to select NAND tree test mode.
To perform a NAND tree test, all pins included in the NAND tree should be driven to 1 except for the following
pins, which use inverting Schmitt trigger inputs and should be driven to 0:
Table 18. Perform NAND Tree Test (Pins Driven To 0)
Pin #
Pin Name
4
IRQ1
5
IRQ8#
6
IOCHK#
10
IRQ9
15
ZEROWS#
32
IRQ7
33
IRQ6
34
IRQ5
56
IRQ4
58
IRQ3
73
IRQ10
75
IRQ11
77
IRQ12
118