82371FB Datasheet, PDF (13/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
1.4. ISA Interface Signals
Signal Name
BALE
Type
O
AEN
O
SYSCLK
O
IOCHRDY
I/O
IOCS16#
I
IOCHK#
I
IOR#
I/O
IOW#
I/O
LA[23:17]/
I/O/
CS1S
O
CS3S
O
CS1P
O
CS3P
O
DA[2:0]
O
Description
BUS ADDRESS LATCH ENABLE: BALE is an active high signal asserted
by the PIIX/PIIX3 to indicate that the address (SA[19:0], LA[23:17]) and
SBHE# signal lines are valid.
ADDRESS ENABLE: AEN is asserted during DMA cycles to prevent I/O
slaves from misinterpreting DMA cycles as valid I/O cycles. This signal is
also driven high during PIIX/PIIX3 initiated refresh cycles.
For the PIIX, when TC is sampled low on the assertion of PWORK (External
DMA mode), the PIIX tri-states this signal.
ISA SYSTEM CLOCK: SYSCLK is the reference clock for the ISA Bus and
drives the bus directly. SYSCLK is generated by dividing PCICLK by 3 or 4.
The SYSCLK frequencies supported are 7.5 MHz and 8.33 MHz. SYSCLK
is a divided down version of PCICLK.
Hardware Strapping Option
SYSCLK is tri-stated when PWROK is negated. The value of SYSCLK is
sampled on the assertion of PWROK: If sampled high, the ISA clock divisor
is 3 (for 25 MHz PCI). If sampled low, the divisor is 4 (for 30 and 33 MHz
PCI).
I/O CHANNEL READY: Resources on the ISA Bus negate IOCHRDY to
indicate that additional time (wait states) is required to complete the cycle.
This signal is normally high on the ISA Bus. IOCHRDY is an input when the
PIIX/PIIX3 owns the ISA Bus and the CPU or a PCI agent is accessing an
ISA slave or during DMA transfers. IOCHRDY is output when an external
ISA Bus Master owns the ISA Bus and is accessing DRAM or a PIIX/PIIX3
register.
16-BIT I/O CHIP SELECT: This signal is driven by I/O devices on the ISA
Bus to indicate that they support 16-bit I/O bus cycles.
I/O CHANNEL CHECK: IOCHK# can be driven by any resource on the ISA
Bus. When asserted, it indicates that a parity or an uncorrectable error has
occurred for a device or memory on the ISA Bus. If enabled, a NMI is
generated to the CPU.
I/O READ: IOR# is the command to an ISA I/O slave device that the slave
may drive data on to the ISA data bus (SD[15:0]).
I/O WRITE: IOW# is the command to an ISA I/O slave device that the slave
may latch data from the ISA data bus (SD[15:0]).
UNLATCHED ADDRESS: The LA[23:17] address lines are bi-directional.
These address lines allow accesses to physical memory on the ISA Bus up
to 16 Mbytes.
The LA[23:17] are also used to drive the IDE interface chip selects and
address lines via an external ALS244 buffer. See the IDE Interface signal
descriptions.
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