82371FB Datasheet, PDF (103/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
Counter 1, Refresh Request Signal
This counter provides the refresh request signal and is typically programmed for mode 2 operation. The
counter negates refresh request for one counter period (838 ns) during each count cycle. The initial count
value is loaded one counter period after being written to the counter I/O address. The counter initially asserts
refresh request, and negates it for 1 counter period when the count value reaches 1. The counter then
asserts refresh request and continues counting from the initial count value.
Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for mode 3 operation. The counter
provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count
value. The speaker must be enabled by a write to port 061h.
3.8. Interrupt Controller
The PIIX/PIIX3 provides an ISA compatible interrupt controller that incorporates the functionality of two
82C59 interrupt controllers. The two controllers are cascaded so that 13 external and three internal interrupts
are possible. The master interrupt controller provides IRQ [7:0] and the slave interrupt controller provides IRQ
[15:8] (Figure 7). The three internal interrupts are used for internal functions only and are not available to the
user. IRQ2 is used to cascade the two controllers together. IRQ0 is used as a system timer interrupt and is
tied to Interval Timer 1, Counter 0. The MIRQ0/IRQ0 pin will function as the IRQ0 output and should be
connected to the INTIN2 input of the IOAPIC when IRQ0 enable bit is set in the MIRQ0 register. IRQ13 is
connected internally to FERR#. The remaining 13 interrupt lines (IRQ[15,14,12:3,1]) are available for external
system interrupts. Edge or level sense selection is programmable on an individual channel by channel basis.
The Interrupt unit also supports interrupt steering. The PIIX/PIIX3 can be programmed to allow the four PCI
active low interrupts (PIRQ[D:A]#) to be internally routed to one of 11 interrupts (IRQ[15,14,12:9,7:3]). In
addition, the motherboard interrupts (MIRQ[1:0] for PIIX and MIRQ0 for PIIX3) may be routed to any of the 11
interrupts.
The Interrupt Controller consists of two separate 82C59 cores. Interrupt Controller 1 (CNTRL-1) and Interrupt
Controller 2 (CNTRL-2) are initialized separately and can be programmed to operate in different modes. The
default settings are: 80x86 Mode, Edge Sensitive (IRQ[15:0]) Detection, Normal EOI, Non-Buffered Mode,
Special Fully Nested Mode disabled, and Cascade Mode. CNTRL-1 is connected as the Master Interrupt
Controller and CNTRL-2 is connected as the Slave Interrupt Controller.
Note that IRQ13 is generated internally (as part of the coprocessor error support) by the PIIX. IRQ12/M is
generated internally (as part of the mouse support) when bit-4 in the XBCS Register is set to a 1. When this
bit is set to a 0, the standard IRQ12 function is provided and IRQ12 appears externally.
IRQ8#
IRQ9
IRQ10
IRQ11
IRQ12/Mouse
FERR#
IRQ14
IRQ15
0#
1
82C59
2
Core
3
4 ^{Controller 2}
5
6
(Slave)
7
INTR
Timer 1
Counter 0
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
0
1
82C59
2
Core
3
4 ^{Controller 1}
5
6
(Master)
7
INTR
(To CPU)
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Figure 7. Block Diagram of the Interrupt Controller
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