82371FB Datasheet, PDF (17/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
1.9. X-Bus Signals
Signal Name
XDIR#
Type
O
XOE#
O
DD15/ PCS# O
BIOSCS#
O
KBCS#
O
RTCCS#
O
RTCALE
O
Description
X-BUS DIRECTION: XDIR# is tied directly to the direction control of a
74F245 that buffers the X-Bus data (XD[7:0]). XDIR# is asserted for all I/O
read cycles, regardless if the accesses are to a PIIX/PIIX3 supported
device. XDIR# is only asserted for memory cycles if BIOS sapce (PIIX and
PIIX3) or APIC space (PIIX3 only) has been decoded. For PCI master
inititated read cycles, XDIR# is asserted from the falling edge of either
IOR# or MEMR# (from MEMR# only if BIOS space (PIIX and PIIX3) or
APIC (PIIX3 only) space has been decoded), depending on the cycle type.
For ISA master-initiated read cycles, XDIR# is asserted from the falling
edge of either IOR# or MEMR# (from MEMR# only if BIOS space has been
decoded), depending on the cycle type. When the rising edge of IOR# or
MEMR# occurs, the PIIX/PIIX3 negates XDIR#. For DMA read cycles from
the X-Bus, XDIR# is asserted from DACKx# falling and negated from
DACKx# rising. At all other times, XDIR# is negated.
X-BUS OUTPUT ENABLE: XOE# is tied directly to the output enable of a
74F245 that buffers the X-Bus data (XD[7:0]) from the system data bus
(SD[7:0]). XOE# is asserted when a PIIX/PIIX3 supported X-Bus device is
decoded, and the devices decode is enabled in the X-Bus Chip Select
Enable Register (XBCS Register). XOE# is asserted from the falling edge
of the ISA commands (IOR#, IOW#, MEMR#, or MEMW#) for PCI Master
and ISA master-initiated cycles. XOE# is negated from the rising edge of
the ISA command signals for CPU and PCI Master-initiated cycles and the
SA[16:0] and LA[23:17] address for ISA master-initiated cycles. XOE# is
not generated during any access to an X-Bus peripheral in which its
decode space has been disabled.
PROGRAMMABLE CHIP SELECT: PCS# is asserted for ISA I/O cycles
that are generated by PCI masters and subtractively decoded to ISA, if the
access hits the address range programmed into the PCSC Register. The
X-Bus buffer signals are enabled when the chip select is asserted (i.e., it is
assumed that the peripheral that is selected via this pin resides on the X-
Bus).
BIOS CHIP SELECT: BIOSCS# is asserted during read or write accesses
to BIOS. BIOSCS# is driven combinatorially from the ISA addresses
SA[16:0] and LA [23:17], except during DMA. During DMA cycles,
BIOSCS# is not generated.
KEYBOARD CONTROLLER CHIP SELECT: KBCS# is asserted during
I/O read or write accesses to KBC locations 60h and 64h. This signal is
driven combinatorially from the ISA addresses SA[16:0] and LA [23:17].
For DMA cycles, KBCS# is never asserted.
REAL TIME CLOCK CHIP SELECT: RTCCS# is asserted during read or
write accesses to RTC location 71h. RTCCS# can be tied to a pair of
external OR gates to generate the real time clock read and write command
signals.
REAL TIME CLOCK ADDRESS LATCH: RTCALE is used to latch the
appropriate memory address into the RTC. A write to port 70h with the
appropriate RTC memory address that will be written to or read from,
causes RTCALE to be asserted. RTCALE is asserted based on IOW#
falling and remains asserted for two SYSCLKs.
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