82371FB Datasheet, PDF (86/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Bit
15:13
12
11:10
9
8
7
6
5:4
3
2
Description
Reserved. Must written as 0s when writing this register.
SuspendR/W. 1=Port in suspend state. 0=Port not in supsend state. This bit should not
be written to a 1 if global suspend is active (bit 3=1 in the USBCMD register). Bit 2 and bit 12
of this register define the hub states as follows:
Bits [12,2]
x0
01
11
Hub Port State
Disable
Enable
Suspend
When in suspend state, downstream progagation of data is blocked on this port, except for
single-ended 0 resets (global reset and port reset). The blocking occurs at the end of the
current transaction if a transaction was in progress when this bit was written to 1. In the
suspend state the port will respond to a resume. Note that the bit status does not change
until the port is suspended and that there may be a delay in suspending a port if there is a
transaction currently in progress on the USB.
Reserved.
Port ResetR/W. 1=Port is in Reset. 0=Port is not in Reset. When in the Reset State, the
port is disabled and sends the USB Reset signaling. Note that host software must guarantee
that the RESET signaling is active for the proper amount of time as specified in the USB
Specification.
Low Speed Device AttachedRO. 1=Low speed device is attached to this port. 0=Full
speed device. Writes have no effect.
ReservedRO. Always read as 1.
Resume DetectRO. 1= Resume detected/driven on port. 0=No resume (K-state)
detected/driven on port. Software sets this bit to a 1 to drive resume signalling. The Host
Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend
state. Note that when this bit is 1, a K-state is driven on the port as long as this bit remains
1 and the port is still in suspend state. Writing a 0 (from 1) causes the port to send a low
speed EOP. This bit remains a 1 until the EOP has completed.
Line StatusRO. These bits reflect the D+ (bit 4) and D- (bit 5) signals lines’ logical levels.
These bits are used for fault detect and recovery as well as for USB diagnostics. This field is
updated at EOF2 time (See chapter 11 of the USB Specification).
Port Enable/Disable ChangeR/WC. 1=Port enabled/disabled status has changed. 0=No
change. For the root hub, this bit gets set only when a port is disabled due to disconnect on
the that port or due to the appropriate conditions existing at the EOF2 point (See chapter 11
of the USB Specification). Software clears this bit by writing a 1 to it.
Port Enabled/DisabledR/W. 1=Enable. 0=Disable. Ports can be enabled by host
software only. Ports can be disabled by either a fault condition (disconnect event or other
fault condition) or by host software. Note that the bit status does not change until the port
state actually changes and that there may be a delay in disabling a port if there is a
transaction currently in progress on the USB.
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