82371FB Datasheet, PDF (29/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

E
82371FB (PIIX) AND 82371SB (PIIX3)
Address
(hex)
00CAh3
00CCh3
00CEh3
00D0h3
00D2h3
00D4h3
00D6h3
00D8h3
00DAh3
00DCh3
00DEh3
00F0h1
FEDC
0000
Address (bits)
BA98 7654
0000
1100
0000
0000
1100
0000
0000
1100
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1101
1101
1101
1101
1101
1101
1101
1101
0000
0000
1111
3210
101x
110x
111x
000x
001x
010x
011x
100x
101x
110x
111x
0000
Type
r/w
r/w
r/w
r/w
wo
wo
wo
wo
wo
wo
r/w
wo
Name
DMA2 CH2 Base and Current
Count
DMA2 CH3 Base and Current
Address
DMA2 CH3 Base and Current
Count
DMA2 Status(r) Command(w)
DMA2 Write Request
DMA2 Write Single Mask Bit
DMA2 Write Mode
DMA2 Clear Byte Pointer
DMA2 Master Clear
DMA2 Clear Mask
DMA2 Read/Write All Mask
Register Bits
Coprocessor Error
Access
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI/ISA
04D0h
0000
0100
1101
0000
r/w
INT-1 edge/level control
PCI/ISA
04D1h
0000
0100
1101
0001
r/w
INT-2 edge/level control
PCI/ISA
0CF9h
0000
1100
1111
1001
r/w
Reset Control
PCI
NOTES:
1. Read and write accesses to these locations are always broadcast to the ISA Bus.
2. Write accesses to these locations are broadcast to the ISA Bus. Read Accesses are not.
PIIX: If programmed in the ISA Controller Recovery Timer register, the PIIX will not alias the 90h-9Fh address range with
the following addresses: 80h, 84−86h, 88h, and 8C−8Eh. In this case accesses to the 90h - 9Fh address range for the
previously specified addresses are forwarded to the ISA Bus for both reads and writes and are ignored during ISA Master
cycles (i.e., They are no-longer considered PIIX registers). Note, that port 92 is always a distinct ISA register and is always
forwarded to the ISA Bus.
PIIX3: If programmed in the ISA Controller Recovery Timer register, the PIIX3 does not alias the entire 90h-9Fh address
range. These locations are considered ISA Bus register locations and not PIIX3 registers.
3. ISA-Compatible DMA register I/O space accesses are always subtractively decoded.
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