82371FB Datasheet, PDF (79/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
2.7.2. BMISTA—BUS MASTER IDE STATUS REGISTER
Address Offset:
Default Value:
Attribute:
Primary Channel—Base + 02h; Secondary Channel—Base + 0Ah
00h
Read/Write Clear
This register provides status information about the IDE device and state of the IDE DMA transfer. Table 8
describes IDE Interrupt Status and Bus Master IDE Active bit states after a DMA transfer has been started.
Bit
Description
7
Reserved. This bit is hardwired to 0.
6
Drive 1 DMA Capable (DMA1CAP)—R/W. 1=Drive 1 is capable of DMA transfers. This bit is a
software controlled status bit that indicates IDE DMA device capability and does not affect
hardware operation.
5
Drive 0 DMA Capable (DMA0CAP)—R/W. 1=Drive 0 is capable of DMA transfers. This bit is a
software controlled status bit that indicates IDE DMA device capability and does not affect
hardware operation.
4:3 Reserved.
2
IDE Interrupt Status—R/WC. This bit, when set to a 1, indicates when an IDE device has
asserted its interrupt line. When bit 2=1, and bit 0=0, i.e. 100b, all read data from the IDE device
has been transferred to main memory and all write data has been transferred to the IDE device.
Software sets this bit to a 0 by writing a 1 to it. IRQ14 is used for the primary channel and
MIRQ0 is used for the secondary channel. IRQ15 is used for the Secondary Channel when
IRQ0 bit, bit5 in the MIRQ0 register, is set. If the interrupt status bit is set to a 0 by writing a 1 to
this bit while the interrupt line (IRQ14 or MIRQ0) is still at the active level, this bit remains 0 until
another assertion edge is detected on the interrupt line.
1
IDE DMA Error—R/WC. This bit is set to 1 when the PIIX/PIIX3 encounters a target abort or
master abort while transferring data on the PCI Bus. Software sets this bit to a 0 by writing a 1
to it.
0
Bus Master IDE Active (BMIDEA)—RO. The PIIX/PIIX3 sets this bit to 1 when bit 0 in the
BMICOM Register is set to 1. The PIIX/PIIX3 sets this bit to 0 when the last transfer for a region
is performed (where EOT for that region is set in the region descriptor). The PIIX/PIIX3 also sets
this bit to 0 when bit 0 of the BMICOM Register is set to 0 or when bit 1 of this register is set to
1. When this bit is read as a zero, all data transferred from the drive during the previous bus
master command is visible in system memory, unless the bus master command was aborted.
Bit 2
0
1
1
Bit 0
1
0
1
Table 8. Interrupt/Activity Status Combinations
Description:
DMA transfer is in progress. No interrupt has been generated by the IDE device.
The IDE device generated an interrupt and the Physical Region Descriptors
exhausted. This is normal completion where the size of the physical memory regions
is equal to the IDE device transfer size.
The IDE device generated an interrupt. The controller has not reached the end of
the physical memory regions. This is a valid completion case when the size of the
physical memory regions is larger than the IDE device transfer size.
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