82371FB Datasheet, PDF (18/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Signal Name
FERR#
Type
I
IGNNE#
od
Description
NUMERIC COPROCESSOR ERROR: This signal is tied to the
coprocessor error signal on the CPU. IGNNE# is only used if the
PIIX/PIIX3 coprocessor error reporting function is enabled in the XBCSA
Register. If FERR# is asserted, the PIIX/PIIX3 generates an internal
IRQ13 to its interrupt controller unit. The PIIX/PIIX3 then asserts the INTR
output to the CPU. FERR# is also used to gate the IGNNE# signal to
ensure that IGNNE# is not asserted to the CPU unless FERR# is active.
FERR# has a weak internal pull-up used to ensure a high level when the
coprocessor error function is disabled.
IGNORE ERROR: This signal is connected to the ignore error pin on the
CPU. IGNNE# is only used if the PIIX/PIIX3 coprocessor error reporting
function is enabled in the XBCSA Register. If FERR# is asserted,
indicating a coprocessor error, a write to the Coprocessor Error Register
(F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until
FERR# is negated. If FERR# is not asserted when the Coprocessor Error
Register is written, the IGNNE# signal is not asserted.
1.10. APIC Bus Signals (PIIX3 Only)
Signal Name
Type
Description
DD14/
I/O
APIC CHIP SELECT (PIIX3 only). This active low output signal is
APICCS#
O
asserted when the APIC Chip Select is enabled and a PCI originated
cycle is positively decoded within the programmed IOAPIC address
space. The default addresses of the IOAPIC are Memory FEC0_0000h
and FEC0_0010h.
System Design Note: The DD[14]/APICCS# signal is demuxed externally
with a 245 transceiver. The output of the transceiver drives the IOAPIC’s
CS# signal. At certain times the transceiver floats its outputs, therefore a
pullup resistor on the output of the tranceiver is required to keep this
signal negated.
TESTIN#/
I
APICREQ#
APIC REQUEST (PIIX3 only). This signal has two functions, depending
on the programming of the APIC Chip Select bit (XBCS Register). See the
Test SIgnal Description for the TESTIN# function. APICREQ# is asserted
by an external APIC device prior to sending an interrupt over the APIC
serial bus. When the PIIX3 samples this pin active it flushes its F-type
DMA buffers pointing towards PCI. Once the buffers are flushed, the
PIIX3 asserts APICACK# to inform the external APIC that it can proceed
to send the APIC interrupt. APICREQ# must be synchronous to PCICLK.
PCIRST#/
O
APICACK#
O
APIC ACKNOWLEDGE (PIIX3 only). This signal has two functions,
depending on the programming of the APIC Chip Select bit (XBCS
Register). See the System Reset Signal Description for the PCIRST#
function. The PIIX3 asserts APICACK# after its internal buffers are
flushed in response to the APICREQ# signal. When the IOAPIC samples
this signal asserted it knows that the PIIX3’s buffers are flushed and that
it can proceed to send the APIC interrupt. The signal is driven from the
rising edge of PCICLK and is negated while PCIRST# is asserted.
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