82371FB Datasheet, PDF (65/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
2.5.1.8.
DMA Base And Current Byte/Word Count Registers (Compatible Segment)
I/O Address:
Default Value:
Attribute:
DMA Channel 0—001h
DMA Channel 4—0C2h
DMA Channel 1—003h
DMA Channel 5—0C6h
DMA Channel 2—005h
DMA Channel 6—0CAh
DMA Channel 3—007h
DMA Channel 7—0CEh
XXXXh (CPURST or Master Clear)
Read/Write
This register determines the number of transfers to be performed. The actual number of transfers is one
more than the number programmed in the Current Byte/Word Count Register When the value in the
register is decremented from zero to FFFFh, a TC is generated. Autoinitialize can only occur when a
TC occurs. If it is not autoinitialized, this register has a count of FFFFh after TC.
For transfers to/from an 8-bit I/O, the Byte/Word count indicates the number of bytes to be transferred.
This applies to DMA channels 0-3. For transfers to/from a 16-bit I/O, with shifted address, the
Byte/Word count indicates the number of 16-bit words to be transferred. This applies to DMA channels
5-7.
Bit
Description
15:0 Base and Current Byte/ Word Count. These bits represent the 16 byte/word count bits used
when counting down a DMA transfer.
2.5.1.9.
DMA Memory Low Page Registers
I/O Address:
Default Value:
Attribute:
DMA Channel 0—087h
DMA Channel 1—083h
DMA Channel 2—081h
DMA Channel 3—082h
XXh (CPURST or Master Clear)
Read/Write
DMA Channel 5—08Bh
DMA Channel 6—089h
DMA Channel 7—08Ah
This register works in conjunction with the Current Address Register. After an autoinitialization, this
register retains the original programmed value. Autoinitialize takes place after a TC.
Bit
Description
7:0 DMA Low Page [23:16]. These bits represent address bits [23:16] of the 24-bit DMA address
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