82371FB Datasheet, PDF (44/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Bit
Description
7
APMC Write SMI Enable. 1=Enable; 0=Disable.
6
EXTSMI# SMI Enable. 1=Enable; 0=Disable.
5
Fast Off Timer SMI Enable. 1=Enable; 0=Disable. When enabled, the timer generates an
SMI when it decrements to zero.
4
IRQ12 SMI Enable (PS/2 Mouse Interrupt). 1=Enable; 0=Disable.
3
IRQ8 SMI Enable (RTC Alarm Interrupt). 1=Enable; 0=Disable.
2
IRQ4 SMI Enable (COM2/COM4 Interrupt or Mouse). 1=Enable; 0=Disable.
1
IRQ3 SMI Enable (COM1/COM3 Interrupt or Mouse). 1=Enable; 0=Disable.
0
IRQ1 SMI Enable (Keyboard Interrupt). 1=Enable; 0=Disable.
2.2.20. SEE—SYSTEM EVENT ENABLE REGISTER (Function 0)
Address Offset:
Default Value:
Attribute:
A4–A7h
00000000h
Read/Write
This register enables hardware events as system events and break events for power management control.
The default for each system/break event in this register is disabled.
System events: Activity by these events can keep the system from powering down. When a system event is
enabled, the corresponding hardware event activity prevents a Fast Off powerdown condition by reloading the
Fast Off Timer with its initial count.
Break events: These events can awaken a powered down system. When a break event is enabled, the
corresponding hardware event activity powers up the system by negating STPCLK#.
Bit
31
30
29
28
27:16
15:3
2
1:0
Description
Fast Off SMI Enable (FSMIEN). 1=Enable (system and break events); 0=Disable.
INTR Enable (FINTREN). 1=Enable (break event); 0=Disable. When enabled, INTR is used
as a global break event. In this case, any IRQ that is generated causes the system to
powerup via the negation of STPCLK#, regardless of the state of bits[15:3,1:0] in this
register.
For the PIIX3, this function should be disabled if an external IOAPIC is used.
Fast Off NMI Enable (FNMIEN). 1=Enable (system and break events); 0=Disable.
82371FB PIIX: Reserved.
PIIX3: Fast Off APIC Enable (FAPICEN). 1=Enable (break event); 0=Disable.
Reserved
Fast Off IRQ[15:3] Enable (FIRQ[15:3]EN). 1=Enable (system and break events);
0=Disable.
Reserved.
Fast Off IRQ[1:0] Enable (FIRQ[1:0]EN). 1=Enable (system and break events); 0=Disable.
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