82371FB Datasheet, PDF (93/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
3.4. DMA Controller
The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven independently
programmable channels (Channels 0-3 and Channels 5-7). DMA Channel 4 is used to cascade the two
controllers and defaults to cascade mode in the DMA Channel Mode (DCM) Register. In addition to accepting
requests from DMA slaves, the DMA controller also responds to requests that are initiated by software.
Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1.
The DMA controller for Channels 0-3 is referred to as "DMA-1" and the controller for Channels 4-7 is referred
to as "DMA-2".
Channel 0
Channel 1
Channel 2
Channel 3
DMA-1
Channel 4
Channel 5
Channel 6
Channel 7
DMA-2
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Figure 2. Internal DMA Controller
Each DMA channel is hardwired to the compatible settings for DMA device size; channels [3:0] are hardwired
to 8-bit count-by-bytes transfers and channels [7:5] are hardwired to 16-bit count-by-words (address shifted)
transfers. The PIIX/PIIX3 provides the timing control and data size translation necessary for the DMA transfer
between the memory (ISA or main memory) and the ISA Bus device. ISA Compatible and F type DMA timing
are supported. Type F DMA is selected via the MBDMA[1:0] Registers and permits up to two channels to be
programmed for type F transfers at the same time.
The PIIX/PIIX3 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel
includes a 16-bit ISA-Compatible Current Register that contains the 16 least-significant bits of the 24-bit
address, an ISA Compatible Page Register that contains the eight next most significant bits of address. The
DMA controller also features refresh address generation, and auto-initialization following a DMA termination.
The DMA controller is either in master or slave mode. In master mode, the DMA controller is either servicing
a DMA slave’s request for DMA cycles or allowing a 16-bit ISA master to use the bus (via a cascaded DREQ
signal). In slave mode, the PIIX/PIIX3 monitors both the ISA Bus and PCI, decoding and responding to I/O
read and write commands that address its registers.
Note that a DMA device (I/O device) is always on the ISA Bus, but the memory referenced is located on
either an ISA Bus device or on PCI. When the PIIX/PIIX3 is running a compatible DMA cycle, it drives the
MEMR# or MEMW# strobes if the address is less than 16 Mbytes (000000–FFFFFFh). These memory
strobes are generated regardless of whether the cycle is decoded for PCI or ISA memory. The SMEMR# and
SMEMW# are generated if the address is less than 1 Mbytes (0000000–00FFFFFh). If the address is greater
than 16 Mbytes (1000000–7FFFFFFh), the MEMR# or MEMW# strobe is not generated in order to avoid
aliasing problems.
The PIIX/PIIX3 drives the AEN signal asserted (high) during DMA cycles to prevent the I/O devices from
misinterpreting the DMA cycle as a valid I/O cycle. The BALE signal is also driven high during DMA cycles.
Also, during DMA memory read cycles to the PCI Bus, the PIIX/PIIX3 the data on the ISA Bus is considered
random if the PCI cycle is either target aborted or master aborted.
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