82371FB Datasheet, PDF (46/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
E
Bit
Description
15:9 Reserved
8
PIIX: Reserved.
PIIX3: Legacy USB SMI Status (RLUSB). This bit is set to 1 to indicate that the USB Legacy
Keyboard logic caused an SMI. Software sets this bit to a 0 by writing a 0 to it.
7
APM SMI Status (RAPMC). This bit is set to 1 to indicate that a write to the APM Control
Register caused an SMI. Software sets this bit to a 0 by writing a 0 to it.
6
EXTSMI# SMI Status (REXT). This bit is set to 1 to indicate that EXTSMI# caused an SMI.
Software sets this bit to a 0 by writing a 0 to it.
For the PIIX3, the EXTSMI# signal can be used to provide a special protocol between the
host-to-PCI bridge and the PIIX3 (see MSTAT Register description, 82h, function 0).
5
Fast Off Timer Expired Status (RFOT). This bit is set to 1 to indicate that the Fast Off Timer
expired and caused an SMI. Software sets this bit to a 0 by writing a 0 to it. Note that the timer
re-starts counting one the next clock after it expires.
4
IRQ12 Request SMI Status (RIRQ12). This bit is set to 1 to indicate that IRQ12 caused an
SMI. Software sets this bit to a 0 by writing a 0 to it.
3
IRQ8# Request SMI Status (RIRQ8). This bit is set to 1 to indicate that IRQ8# caused an
SMI. Software sets this bit to a 0 by writing a 0 to it.
2
IRQ4 Request SMI Status (RIRQ4). This bit is set to 1 to indicate that IRQ4 caused an SMI.
Software sets this bit to a 0 by writing a 0 to it.
1
IRQ3 Request SMI Status (RIRQ3). This bit is set to 1 to indicate that IRQ3 caused an SMI.
Software sets this bit to a 0 by writing a 0 to it.
0
IRQ1 Request SMI Status (RIRQ1). This bit is set to 1 to indicate that IRQ1 caused an SMI.
Software sets this bit to a 0 by writing a 0 to it.
2.2.23. CTLTMR—CLOCK SCALE STPCLK# LOW TIMER (Function 0)
Address Offset:
Default Value:
Attribute:
ACh
00h
Read/Write
The value in this register defines the duration of the STPCLK# asserted period when bit 2 in the SMICNTL
Register is set to 1. The value in this register is loaded into the STPCLK# Timer when STPCLK# is asserted.
The STPCLK# timer is a divide by PCI clock. The base count for a value of 0 is 42 µsec for a 50 MHz time
base, 35 µsec for a 60 MHz time base, 32 µsec for a 66 MHz time base. These numbers are determined as
follows: # of PCI clocks STPCLK# is asserted (or negated) = 1 + 1056 X (programmed value in register +1).
Bit
Description
7:0
Clock Scaling STPCLK# Low Timer Value. Bits [7:0] define the duration of the STPCLK#
asserted period during clock throttling.
46