82371FB Datasheet, PDF (21/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
1.15. Signal State During Reset
Table 1 shows the state of all PIIX/PIIX3 output and bi-directional signals during a hard reset. A hard reset is
initiated when PWROK is asserted or by programming a hard reset through the RC Register.
Table 1. Output and I/O Signal States During Hard Reset
Signal
State
Signal
State
Signal
State
AD[31:0]
Low (PIIX)
LA23/CS1S
Undefined
PIRQD# (PIIX3) Tri-state
Tri-State
(PIIX3)
C/BE[3:0]#
Low (PIIX)
Tri-State
(PIIX3)
FRAME#
Tri-state
TRDY#
Tri-state
IRDY#
Tri-state
STOP#
Tri-state
DEVSEL#
Tri-state
PAR
Input
PHOLD#
High (PIIX)
Tri-state
(PIIX3)
MDAK[1:0]#
(PIIX)
High
DD[15,13:0]/
PCS#,SBHE#,
SA[19:8],
DD14 (PIIX)
Tri-state
DD14 (PIIX) Tri-state
DD14/APICCS# High
(PIIX3)
SA[7:0]
Undefined
DIOR#
High
DIOW#
High
DDAK[1:0]#
High
SOE#
High
SDIR
High
LA22/CS3S
Undefined
LA21/CS1P
Undefined
LA20/CS3P
Undefined
LA[19:17]/
DA[2:0]
Undefined
BALE
Low
AEN
Depends on
strapping
option
SYSCLK
Strapping
Option
IOCHRDY
Tri-state
IOR#
High
IOW#
High
MEMCS16# Open drain
MEMR#
Tri-state
MEMW#
Tri-state
SMEMR#
High
SMEMW#
High
SD[15:0]
Tri-state
DACK[7:5,3:0]# Depends on
strapping
option
TC
Strapping
Option
REFRESH#
Tri-state
SPKR
Low
INTR
Open drain
NMI
Open drain
SMI#
Open drain
STPCLK#
Open drain
XDIR#
High
XOE#
High
BIOSCS#
Undefined
(PIIX)
High (PIIX3)
KBCS#
Undefined
(PIIX)
High (PIIX3)
RTCCS#
Undefined
(PIIX)
High (PIIX3)
RTCALE
Low
FERR#
Open drain
IGNNE#
Open drain
CPURST
Open drain
USBP0+
USBP0-
Tri-state
USBP1+
USBP1-
Tri-state
PCIRST# (PIIX) Low
PCIRST#/
APICACK#
(PIIX3)
INIT
Low
RSTDRV
High
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