82371FB Datasheet, PDF (19/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
1.11. Universal Serial Bus Signals (PIIX3 Only)
Signal Name
USBCLK
USBP0+
USBP0-
USBP1+
USBP1-
Type
I
I/O
I/O
Description
UNIVERSAL SERIAL BUS CLOCK. This signal clocks the universial serial
bus clock.
UNIVERSAL SERIAL BUS PORT 0. These signals are the differential data
pair for Serial Port 0.
UNIVERSIAL SERIAL BUS PORT 1. These signals are the differential data
pair for Serial Port 1.
1.12. System Reset Signals
Signal Name
PWROK
CPURST
PCIRST#/
APICACK#
(PIIX3 Only)
INIT
RSTDRV
Type
I
od
O
O
OD
O
Description
POWER OK: When asserted, PWROK is an indication to the PIIX/PIIX3
that power and PCICLK have been stable for at least 1 ms. PWROK can be
driven asynchronously. When PWROK is negated, the PIIX/PIIX3 asserts
CPURST, PCIRST# and RSTDRV. When PWROK is asserted, the
PIIX/PIIX3 negates CPURST, PCIRST#, and RSTDRV.
CPU RESET: The PIIX/PIIX3 asserts CPURST to reset the CPU. The
PIIX/PIIX3 asserts CPURST during power-up and when a hard reset
sequence is initiated through the RC register. CPURST is driven
synchronously to the rising edge of PCICLK. If a hard reset is initiated
through the RC register, the PIIX/PIIX3 resets it’s internal registers to the
default state.
PCI RESET: This signal has two functions, depending on the programming
of the APIC Chip Select bit (XBCS Register). See the APIC SIgnal
Description for the APICACK# function. The PIIX/PIIX3 asserts PCIRST# to
reset devices that reside on the PCI Bus. The PIIX/PIIX3 asserts PCIRST#
during power-up and when a hard reset sequence is initiated through the
RC register. PCIRST# is driven inactive a minimum of 1 ms after PWROK
is driven active. PCIRST# is driven active for a minimum of 1ms when
initiated through the RC register. PCIRST# is driven asynchronously
relative to PCICLK.
INITIALIZATION: The PIIX/PIIX3 asserts INIT if it detects a shut down
special cycle on the PCI Bus or if a soft reset is initiated via the RC
Register.
RESET DRIVE: The PIIX/PIIX3 asserts this signal during a hard reset and
during power-up to reset ISA Bus devices. RSTDRV is also asserted for a
minimum of 1 ms if a hard reset has been programmed in the RC Register.
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