82371FB Datasheet, PDF (36/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

82371FB (PIIX) AND 82371SB (PIIX3)
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2.2.10. PIRQRC[A:D]—PIRQx ROUTE CONTROL REGISTERS (Function 0)
Address Offset :
Default Value:
Attribute:
60h (PIRQRCA#)—63h (PIRQRCD#)
80h
R/W
These registers control the routing of the PIRQ[A:D]# signals to the IRQ inputs of the interrupt controller.
Each PIRQx# can be independently routed to any one of 11 interrupts. All four PIRQx# lines can be routed to
the same IRQx input. Note that the IRQ that is selected through bits [3:0] must be set to level sensitive mode
in the corresponding ELCR Register. When a PIRQ signal is routed to an interrupt controller IRQ, the
PIIX/PIIX3 masks the corresponding IRQ signal.
Bit
Description
7
Interrupt Routing Enable. 0=Enable; 1=Disable
6:4 Reserved. Read as 0s.
3:0 Interrupt Routing. When bit 7=0, this field selects the routing of the PIRQx to one of the
interrupt controller interrupt inputs.
Bits[3:0]
0000
0001
0010
0011
0100
0101
IRQ Routing
Reserved
Reserved
Reserved
IRQ3
IRQ4
IRQ5
Bits[3:0]
0110
0111
1000
1001
1010
IRQ Routing
IRQ6
IRQ7
Reserved
IRQ9
IRQ10
Bits[3:0]
1011
1100
1101
1110
1111
IRQ Routing
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
2.2.11. TOM—TOP OF MEMORY REGISTER (Function 0)
Address Offset:
Default Value:
Attribute:
69h
02h
Read/Write
This register enables the forwarding of ISA or DMA memory cycles to the PCI Bus and sets the top of main
memory accessible by ISA or DMA devices. In addition, this register controls the forwarding of ISA or DMA
accesses to the lower BIOS region (E0000–EFFFFh) and the 512–640-Kbyte main memory region (80000–
9FFFFh). The Top Of Memory configuration register must be set by the BIOS.
Bit
7:4
Description
Top Of Memory. The top of memory can be assigned in 1-Mbyte increments from 1–16
Mbytes. ISA or DMA accesses within this region, and not in the memory hole region, are
forwarded to PCI.
Bits[7:4] Top of Memory Bits[7:4] Top of Memory Bits[7:4] Top of Memory
0000
0001
0010
0011
0100
0101
1 Mbyte
2 Mbyte
3 Mbyte
4 Mbyte
5 Mbyte
6 Mbyte
0110
0111
1000
1001
1010
7 Mbyte
8 Mbyte
9 Mbyte
10 Mbyte
11 Mbyte
1011
1100
1101
1110
1111
12 Mbyte
13 Mbyte
14 Mbyte
15 Mbyte
16 Mbyte
Note that the PIIX/PIIX3 only supports a main memory hole at the top of 16 Mbytes. Thus, If
a 1-Mbyte memory hole is created for the Host-to-PCI Bridge DRAM controller between 15
and 16 Mbytes, the PIIX/PIIX3 Top Of Memory should be set at 15 Mbytes.
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