82371FB Datasheet, PDF (51/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
2.3.10. IDETIM—IDE TIMING REGISTER (Function 1)
Address Offset:
Default Value:
Attribute:
Primary Channel=40–41h; Secondary Channel=42–43h
0000h
Read / Write Only
This register controls the PIIX's IDE interface and selects the timing characteristics of the PCI Local Bus IDE
cycle. Note that primary and secondary denotations distiguish between the cables and the 0/1 denotations
distiguish between master (0) and slave (1).
Bit
15
14
13:12
11:10
9:8
7
6
5
Description
IDE Decode Enable (IDE). 1=Enable; 0=Disable. When enabled, I/O transactions on PCI
targeting the IDE ATA register blocks (command block and control block) are positively
decoded on PCI and driven on the IDE interface. When disabled, these accesses are
subtractively decoded to ISA.
PIIX: Reserved.
PIIX3: Slave IDE Timing Register Enable (SITRE). 1=Enable SIDETIM Register. 0=Disable
(default) SIDETIM Register. When enabled, the ISP and RTC values can be programmed
uniquely for each master through the fields in this register and these values can be
programmed for each slave through the SIDETIM Register. When disabled, the ISP and RTC
values programmed in this register apply to both master and slave drives on each channel.
IORDY Sample Point (ISP). This field selects the number of clocks between DIOx#
assertion and the first IORDY sample point.
Bits[13:12]
00
01
10
11
Number Of Clocks
5
4
3
2
Reserved
Recovery Time (RTC). This field selects the minimum number of clocks between the last
IORDY# sample point and the DIOx# strobe of the next cycle.
Bits[9:8]
00
01
10
11
Number Of Clocks
4
3
2
1
DMA Timing Enable Only (DTE1). When DTE1=1, fast timing mode is enabled for DMA
data transfers for drive 1. Note that PIO transfers to the IDE data port still run in compatible
timing.
Prefetch and Posting Enable (PPE1). When PPE1=1, prefetch and posting to the IDE data
port is enabled for drive 1.
IORDY Sample Point Enable Drive Select 1 (IE1). When IE1=0, IORDY sampling is
disabled for Drive 1. The internal IORDY signal is forced asserted guaranteeing that IORDY
is sampled asserted at the first sample point as specified by the ISP field in this register.
When IE1=1 and the currently selected drive (via a copy of bit 4 of 1x6h) is Drive 0, all
accesses to the enabled I/O address range sample IORDY. The IORDY sample point is
specified by the ISP field in this register.
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