82371FB Datasheet, PDF (91/122 Pages) Intel Corporation – 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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82371FB (PIIX) AND 82371SB (PIIX3)
PIIX/PIIX3 As a Master—Response to Target-Initiated Termination: As a master, the PIIX/PIIX3 responds
in one of three ways to a target-termination Target-Abort, Retry, or Disconnect.
PIIX/PIIX3 As a Target—Target-Initiated Termination: The PIIX/PIIX3 supports three forms of Target-
initiated Termination  Disconnect, Retry, Target Abort.
3.2.2. PARITY SUPPORT
As a master, the PIIX/PIIX3 generates address parity for read/write cycles and data parity when the
PIIX/PIIX3 is providing the data. As a slave, the PIIX/PIIX3 generates data parity for read cycles. The
PIIX/PIIX3 does not check parity and does not generate SERR#. However, the PIIX/PIIX3 does generate an
NMI when another PCI device asserts SERR# (if enabled).
PAR is the calculated parity signal. PAR is even parity and is calculated on 36 bits—AD[31:0] signals plus
C/BE[3:0]#.PAR is always calculated on 36 bits, regardless of the valid byte enables. PAR is only guaranteed
to be valid one PCI clock after the corresponding address or data phase.
3.2.3. PCI ARBITRATION
The PIIX/PIIX3 requests the use of the PCI Bus on behalf of ISA devices (bus masters and DMA) and IDE
DMA slave devices using the PHOLD# and PHLDA# signals. These signals connect to the Host-to-PCI
Bridge where the PCI arbiter is located.
ISA devices (Bus Master or DMA) assert DREQ to gain access to the ISA Bus. In response, The PIIX/PIIX3
asserts PHOLD#. The PIIX/PIIX3 keeps DACK negated until the PIIX/PIIX3 has ownership of the PCI Bus
and Memory. The PCI arbiter asserts PHLDA# to the PIIX/PIIX3 when the above conditions are met. The
PIIX/PIIX3 gives ownership of the ISA Bus (PCI and Memory) to the ISA device after sampling PHLDA#
asserted.
Arbitration
The PIIX/PIIX3 requests the use of PCI bus on behalf of ISA devices, IDE Masters and USBHC channels.
The PIIX/PIIX3 arbitrates for the PCI bus through the PHOLD# and PHLDA# signals. The ISA DMA/Master
channels, the IDE bus master channels and USBHC channels are arbitrated fairly as a group (fairness
between three groups).
Multiple Transactions on PCI Bus (PIIX3 Only)
The USB module utilizes the arbitration advantage available through the PHOLD#/PHLDA# to do multiple
transactions on the PCI bus once it has the ownership of the bus and the MLT count has not expired. The
USBHC relinquishes the bus ownership as soon the transactions are completed or the MLT counter has
expired, whichever happens first. Refer to the DLC register description for information on delayed completion
and passive release.
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