GS4901B_09 Datasheet, PDF (94/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

4. Application Reference Design
4.1 GS4901B Typical Application Circuit
JTAG/HOSTb
SCLK
SDIN
SDOUT
CSb
RESETb
GENLOCKb
LOCK_LOST
REF_LOST
38pF
24pF
GND_XTAL
27MHz
1M
0R
VDD_XTAL
10n
1V8_VPLL
10n
GND_VPLL
GND_XTAL
1V8_APLL
10n
The 10FID input must be
grounded if it will not be used
10FID
HSYNC
VSYNC
FSYNC
GND_APLL
NOTE: The GS4911A inputs are 5V tolerant for
3V3 I/O operation only (IO_VDD=3V3)
VID_STD0
VID_STD1
VID_STD2
VID_STD3
VDD_IO
10n
1V8_VPLL
10n
GND_VPLL
VDD_IO
10n
1V8_PCLK
10n
22R
22R
Controlled impedance
100-ohms differential
1
LOCK_LOST
2
REF_LOST
3
VID_PLL_VDD
4
VID_PLL_GND
5
XTAL_VDD
6
X1
7
X2
8
XTAL_GND
9
CORE_GND
10
ANALOG_VDD
11
NC
12
ANALOG_GND
13
AUD_PLL_GND
14
AUD_PLL_VDD
15
10FID
16
HSYNC
65
GND_PAD
VDD_IO
1V8_CORE _10n
GS4901B
48
LVDS/PCLK3_GND
47
PCLK3
46
PCLK3
45
LVDS/PCLK3_VDD
44
CORE_VDD
43
TIMING_OUT8
42
TIMING_OUT7
41
TIMING_OUT6
40
TIMING_OUT5
39
TIMING_OUT4
38
IO_VDD
37
TIMING_OUT3
36
TIMING_OUT2
35
TIMING_OUT1
34
ASR_SEL0
33
ASR_SEL1
1V8_PCLK
1V8_CORE
VDD_IO
10n
10n
10n
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
10n
10n
PCLK1
PCLK2
PCLK3
PCLK3b
TIMING8
TIMING7
TIMING6
TIMING5
TIMING4
TIMING3
TIMING2
TIMING1
ACLK1
ACLK2
ACLK3
ASR_SEL0
ASR_SEL1
ASR_SEL2
NOTE: For a solution with the lowest output jitter, the GS9062 or GS9092A serializers are
recommended for use with the GS4901B/GS4900B.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
94 of 102