GS4901B_09 Datasheet, PDF (42/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

3.5 Reference Format Detector
The reference format detector checks the validity and analyzes the format of the input
reference signal. It is designed to accurately differentiate between 59.94 and 60Hz
frame rates.
As described in Section 1.4 on page 19, the GS4901B / GS4900B will automatically
recognize the SD video standards defined by VID_STD[5:0] = 1 to 10. However, in order
to enable the device to recognize and lock to any of the HD reference formats defined
by VID_STD[5:0] = 11 to 38, the user must set the corresponding bit LOW in the
Reference_Standard_Disable register, located at address 11h-13h of the host interface.
The user must also set the HD_Reference_Enable bit of register 82h[7] HIGH. See the
description of the Reference_Standard_Disable and HD_Reference_Enable registers in
Section 3.10.3 on page 67.
3.5.1 Horizontal and Vertical Timing Characteristic Measurements
When a reference signal is applied to the designated input pins, the GS4901B/GS4900B
will analyse the signal and report the following in registers 0Ah to 0Eh of the host
interface:
• the number of 27MHz clock pulses between leading edges of the H input reference
signal (H_Period register)
• the number of 27MHz clock pulses in 16 horizontal periods (H_16_Period register)
• the number of H reference pulses between leading edges of the V input reference
signal (V_Lines register)
• the number of H reference pulses in two vertical periods (V_2_Lines register)
• the number of H reference pulses in one F period (F_Lines register)
These parameters may be read via the host interface and are used by the device to
determine reference signal validity.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
42 of 102