GS4901B_09 Datasheet, PDF (93/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Application HOST
GS4911B/GS4910B
CS_TMS
SCLK_TCLK
SDIN_TDI
Tri-State
Figure 3-17: System JTAG
3.12 Device Power-Up
In-circuit ATE probe
SDOUT_TDO
JTAG/HOST
3.12.1 Power Supply Sequencing
The GS4901B/GS4900B has a recommended power supply sequence. To ensure correct
power-up, the ANALOG_VDD and CORE_VDD power pins should be powered before
IO_VDD.
Device pins may be driven prior to power-up without causing damage.
3.13 Device Reset
In order to initialize operating conditions to their default states, the application layer
must hold the RESET signal LOW during power up and for a minimum of 500us after the
last supply has reached its operating voltage.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
93 of 102