GS4901B_09 Datasheet, PDF(71/102 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GS4901B_09 Datasheet, PDF (71/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

◁

Table 3-13: Configuration and Status Registers (Continued)

Genlock_Control

RSVD

Address

16h

17h-19h

Bit

15-7

Description

R/W

Reserved. Set these bits to zero when writing to

16h.

This bit is used to enable the Extended Audio Mode R/W

of the device.

Genlock_From_Host - set this bit HIGH to enable

R/W

video genlock control via the Host Interface instead

of the external GENLOCK pin (see bit 0 of this

Reference: Section 3.2 on page 35

F_Lock_Mask - if this bit is set HIGH, the

R/W

GS4901B/GS4900B will ignore the status of F_Lock

(bit 4 of register 15h) when determining the status

of Reference_Lock (bit 5 of register 15h).

Reference: Section 3.6.1 on page 49

V_Lock_Mask - if this bit is set HIGH, the

R/W

GS4901B/GS4900B will ignore the status of V_Lock

(bit 3 of register 15h) when determining the status

of Reference_Lock (bit 5 of register 15h).

Reference: Section 3.6.1 on page 49

H_Lock_Mask - if this bit is set HIGH, the

R/W

GS4901B/GS4900B will ignore the status of H_Lock

(bit 2 of register 15h) when determining the status

of Reference_Lock (bit 5 of register 15h).

Reference: Section 3.6.1 on page 49

Drift_Crash - when this bit is set HIGH, the

R/W

generated video clock will drift lock to a new input

reference rather than crash lock.

Reference: Section 3.6.1 on page 49

GENLOCK - this bit may be used instead of the

R/W

external pin to Genlock the output video format to

the input reference. This bit will be ignored if bit 5

of this register is LOW.

Reference: Section 3.2 on page 35

Reserved

Default

GS4901B/GS4900B SD Clock and Timing Generator

with GENLOCK

Data Sheet

37703 - 4

December 2009

71 of 102

▷