GS4901B_09 Datasheet, PDF (87/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
V_Start_2
V_Stop_2
Operator_Polarity_2
Address
5Eh
5Eh
5Fh
5Fh
60h
60h
60h
60h
60h
Bit
15
14-0
15
14-0
15-4
3
2
1
0
Description
R/W
Reserved. Set this bit to zero when writing to 5Eh. –
The value programmed in this register indicates the R/W
start line number of the leading edge of the
user-programmed V Sync signal USER2_V. For
interlaced output standards, this value corresponds
to the odd field line number.
NOTE: The value programmed in this register must
be less than the value programmed in V_Stop_2.
Reference: Section 3.8.3 on page 60
Reserved. Set this bit to zero when writing to 5Fh. –
The value programmed in this register indicates the R/W
end line number of the trailing edge of the
user-programmed V Sync signal USER2_V. For
interlaced output standards, this value corresponds
to the odd field line number.
NOTE: The value programmed in this register must
not exceed the maximum number of lines per field
of the outgoing standard.
Reference: Section 3.8.3 on page 60
Reserved. Set these bits to zero when writing to
–
60h.
Polarity_2 - Use this bit to invert the polarity of the R/W
final USER2 signal.
By default, the polarity of the user programmed
signals is active LOW. The polarity may be switched
to active HIGH by setting this bit LOW.
Reference: Section 3.8.3 on page 60
AND_2 - logical operator: USER2_H AND USER2_V
R/W
Set this bit HIGH to output a signal that is only
active when both USER2_H and USER2_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register
will be ignored.
Reference: Section 3.8.3 on page 60
OR_2 - logical operator: USER2_H OR USER2_V
R/W
Set this bit HIGH to output a signal that is active
whenever USER2_H or USER2_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference: Section 3.8.3 on page 60
XOR_2 - logical operator: USER2_H XOR USER2_V
R/W
Set this bit HIGH to output a signal with the
following attributes: Signal becomes active when
either USER2_H or USER2_V is active. Signal is
inactive when USER2_H and USER2_V are both
active or both inactive.
Reference: Section 3.8.3 on page 60
Default
–
0
–
0
–
1
0
0
0
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
87 of 102