GS4901B_09 Datasheet, PDF(73/102 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B_09 Datasheet, PDF (73/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers (Continued)

V_Offset

Clock_Phase_Offset

Max_Ref_Delta

Address

1Ch

1Dh

1Eh

Bit

15-0

Description

R/W

The output V signal may be delayed with respect to R/W

the input reference by the number of lines

programmed in this register. (See Section 3.2.1.1 on

page 36).

The value programmed in this register should not

exceed the maximum number of lines per frame of

the outgoing standard. Vertical advances may be

achieved by programming a value equal to the

maximum allowable offset minus the desired

advance.

NOTE: This register is internally read by the device

once per field. At that time any new value

programmed is sent to the internal offset circuitry.

Reference: Section 3.2.1.1 on page 36

Phase_Offset - The output clock and data phase may R/W

be offset with respect to the input reference by the

number of increments programmed in this register.

The increment step size depends on the video clock

frequency.

The encoding scheme for this register is shown in

Table 3-1.

NOTE: This register must be cleared to achieve a

clock phase offset of zero.

Reference: Section 3.2.1.1 on page 36

The value programmed in this register controls the R/W

allowed deviance from the expected frequency on

the reference HSYNC before the internal video PLL

loses lock. The encoding scheme is shown in

Table 3-3.

Reference: Section 3.5.4 on page 47

Default

000Bh

GS4901B/GS4900B SD Clock and Timing Generator

with GENLOCK

Data Sheet

37703 - 4

December 2009

73 of 102

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