GS4901B_09 Datasheet, PDF (76/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Video_Res_Genlock
RSVD
PCLK1_Phase/Divide
Address
27h
27h
28h-2Bh
2Ch
2Ch
2Ch
2Ch
2Ch
Bit
15-6
5-0
–
15-7
6
5-2
1
0
Description
R/W
Reserved. Set these bits to zero when writing to
–
27h.
Control signal to adjust loop bandwidth of video
R/W
genlock block.
The value programmed in this register must be
between 32 and 42.
The default value of this register will vary
depending on the output video standard selected.
Reference: Section 3.6.2 on page 49
Reserved
–
Reserved. Set these bits to zero when writing to
–
2Ch.
Current_P1 - selects the current drive capability of R/W
the PCLK1 pin. Set this bit HIGH for high current
drive. Otherwise, the current drive will be low.
Reference: Section 3.7.1 on page 52
PCLK1_Phase - adjusts the output phase of the
R/W
PCLK1 clock with respect to the timing output pins.
Phase is delayed in 700ps (nominal) increments as
shown in Table 3-6.
Reference: Section 3.7.1 on page 52
Divide_By_4 - set this bit HIGH to divide the output R/W
PCLK1 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK1 pin LOW.
Reference: Section 3.7.1 on page 52
Divide_By_2 - set this bit HIGH to divide the output R/W
PCLK1 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK1 pin LOW.
Reference: Section 3.7.1 on page 52
Default
–
–
–
–
0
0
0
0
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
76 of 102