GS4901B_09 Datasheet, PDF(86/102 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B_09 Datasheet, PDF (86/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers (Continued)

Operator_Polarity_1

H_Start_2

H_Stop_2

Address

5Bh

5Ch

5Dh

Bit

15-4

15-0

Description

R/W

Reserved. Set these bits to zero when writing to

5Bh.

Polarity_1 - Use this bit to invert the polarity of the R/W

final USER1 signal.

By default, the polarity of the user programmed

signals is active LOW. The polarity may be switched

to active HIGH by setting this bit LOW.

Reference: Section 3.8.3 on page 60

AND_1 - logical operator: USER1_H AND USER1_V

R/W

Set this bit HIGH to output a signal that is only

active when both USER1_H and USER1_V are active.

When this bit is HIGH, bit 1 and bit 0 of this register

will be ignored.

Reference: Section 3.8.3 on page 60

OR_1 - logical operator: USER1_H OR USER1_V

R/W

Set this bit HIGH to output a signal that is active

whenever USER1_H or USER1_V are active.

When this bit is HIGH bit 0 of this register will be

ignored.

Reference: Section 3.8.3 on page 60

XOR_1 - logical operator: USER1_H XOR USER1_V

R/W

Set this bit HIGH to output a signal with the

following attributes: Signal becomes active when

either USER1_H or USER1_V is active. Signal is

inactive when USER1_H and USER1_V are both

active or both inactive.

Reference: Section 3.8.3 on page 60

The value programmed in this register indicates the R/W

pixel start point for the leading edge of the

user-programmed H Sync signal USER2_H.

NOTE: The value programmed in this register must

be less than the value programmed in H_Stop_2

Reference: Section 3.8.3 on page 60

The value programmed in this register indicates the R/W

pixel end point for the trailing edge of the

user-programmed H Sync signal USER2_H.

NOTE: The value programmed in this register must

not exceed the maximum number of clock periods

per line of the outgoing standard.

Reference: Section 3.8.3 on page 60

Default

GS4901B/GS4900B SD Clock and Timing Generator

with GENLOCK

Data Sheet

37703 - 4

December 2009

86 of 102

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