GS4901B_09 Datasheet, PDF (56/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

625i 50 Format
For the 48kHz sampling rate, the audio to video phase relationship for 625/50i reference
signals is provided by the device in accordance with the EBU recommended practice
R83-1996. The start of an audio frame (fs clock) will align with the 50% point of the H
sync input of line 1 of each video frame (+/- the allowable drift specified in Table 3-9).
525i 59.94 Format
For 525/59.94 NTSC reference signals, the device will observe the 5-frame
phase-relationship inherent with this video standard, aligning the audio clocks with the
50% point of the H sync input of line 1 on every fifth frame (+/- the allowable drift
specified in Table 3-9).
The number of audio sample clocks during a video frame is shown in Table 3-10 for 32,
44.1, and 48kHz audio sampling frequencies.
Table 3-10: Audio Sampling Frequency to Video Frame Rate Synchronization
Audio Sample Rate (kHz)
32
44.1
48
* fps = frames per second.
24fps
4000/3
3675/2
2000
25fps
1280
1764
1920
Audio Samples per Video Frame
29.97fps
16016/15
147147/100
8008/5
30fps
3200/3
1470
1600
50fps
640
882
960
59.94fps
8008/15
147147/200
4004/5
60fps
1600/3
735
800
The external 10FID input pin may be used to resynchronize other audio clock
frequencies, according to Table 3-10, by applying an active signal during the reference
HSYNC of line 1 of the appropriate video frame. Please see Section 3.4.2 on page 42 for
more details on the 10FID input pin.
In the case where 10FID is not present as a reference signal, the GS4901B will
automatically generate an AFS pulse appropriate to the format selected, and use it to
create an audio frame sequence.
Host Interface Control of AFS and 10FID
Alternatively, the user may program the device via the host interface to re-time the
audio frame sequence and 10 field-ID. Using register 1Ah, a pulse may be generated to
reset the AFS and/or 10FID dividers at the start of an output video frame (see
Section 3.10.3 on page 67).
If using the host interface to reset the AFS pulse, the device may be configured to ignore
the input 10FID reference pin. To disable the signal on the external 10FID pin from
resetting the AFS output pulse, set bit 0 of the Audio_Control register HIGH.
If using the host interface to reset the 10FID pulse, the external 10FID pin must be
grounded.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
56 of 102