GS4901B_09 Datasheet, PDF (83/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Output_Select_8
RSVD
Video_Control
VID_STD[5:0]
RSVD
Polarity
Address
4Ah
4Ah
4Ah
4Bh
4Ch
4Ch
4Ch
4Ch
4Ch
4Dh
4Dh
4Eh-55h
56h
Bit
15-5
4
3-0
–
15-5
4
3-2
1
0
15-6
5-0
–
15-10
Description
R/W
Reserved. Set these bits to zero when writing to
–
4Ah.
Current_8 - selects the current drive capability of
R/W
the TIMING_OUT_8 pin. Set this bit HIGH for high
current drive. Otherwise, the current drive will be
low.
Reference: Section 3.8.4 on page 62
This register is used to select one of the 10
R/W
pre-programmed or 4 user programmed timing
signals available for output on the TIMING_OUT_8
pin. See Table 3-11 for more details.
Note: The default setting of this register is 1000b,
which corresponds to Display Enable (DE).
Reference: Section 3.8.4 on page 62
Reserved.
–
Reserved. Set these bits to zero when writing to
–
4Ch.
10FID_F_pulse - set this bit HIGH to stretch the 10FID R/W
pulse duration from 1 line to 1 field.
Reference: Section 3.8.1 on page 58
Reserved. Set these bits to zero when writing to
–
4Ch.
Host_VID_STD - set this bit HIGH to select the
R/W
output video standard using register 4Dh instead of
the external VID_STD[5:0] pins.
The external VID_STD[5:0] pins will be ignored, but
should not be left floating.
Reference: Section 1.4 on page 19
Reserved. Set this bit to zero when writing to 4Ch. –
Reserved. Set these bits to zero when writing to
–
4Dh.
Replaces the external VID_STD[5:0] pins when
R/W
VID_From_Host (bit 1 of address 4Ch) is HIGH.
Reference: Section 1.4 on page 19
Reserved
–
Reserved. Set these bits to zero when writing to
–
56h.
Default
–
0
1000b
–
–
0
–
0
–
–
00h
–
–
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
83 of 102