GS4901B_09 Datasheet, PDF (84/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Polarity
Address Bit
56h
9
56h
8
56h
7
56h
6
56h
5
56h
4
56h
3
56h
2
Description
R/W
AFS (GS4901B only)- set this bit HIGH to invert the R/W
polarity of the AFS timing output signal.
By default, the AFS signal is HIGH for the duration
of the first line of the n’th video frame to indicate
that the ACLK dividers have been reset at the start
of line 1 of that frame.
NOTE: The GS4900B does not generate an AFS pulse
and will ignore the setting of this bit.
Reference: Table 1-3
10FID - set this bit HIGH to invert the polarity of the R/W
10FID timing output signal.
By default, the 10FID signal will go HIGH for one
line at the start of the 10-field sequence.
Reference: Table 1-3
DE - set this bit HIGH to invert the polarity of the DE R/W
timing output signal.
By default, the DE signal will be HIGH whenever
pixel information is to be displayed on the display
device
Reference: Table 1-3
Reserved. Set this bit to zero when writing to 56h. –
F_Digital - set this bit HIGH to invert the polarity of R/W
the F Digital timing output signal.
By default, the F Digital signal will be HIGH for the
entire period of field 1.
Reference: Table 1-3
F_Sync - set this bit HIGH to invert the polarity of
R/W
the F Sync timing output signal.
By default, the F Sync signal will be HIGH for the
entire period of field 1.
Reference: Table 1-3
V_Blanking - set this bit HIGH to invert the polarity R/W
of the V Blanking timing output signal.
By default, the V Blanking signal will be LOW for
the portion of the field/frame containing valid
video data.
Reference: Table 1-3
V_Sync - set this bit HIGH to invert the polarity of
R/W
the V Sync timing output signal.
By default, the V Sync signal is active LOW.
Reference: Table 1-3
Default
0
0
0
–
0
0
0
0
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
84 of 102