GS4901B_09 Datasheet, PDF(77/102 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B_09 Datasheet, PDF (77/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers (Continued)

PCLK2_Phase/Divide

PCLK3_Phase/Divide

PCLK3_Tristate

Address

2Dh

2Eh

2Fh

Bit

15-7

5-2

15-6

5-2

15-2

1-0

Description

R/W

Reserved. Set these bits to zero when writing to

2Dh.

Current_P2 - selects the current drive capability of R/W

the PCLK2 pin. Set this bit HIGH for high current

drive. Otherwise, the current drive will be low.

Reference: Section 3.7.1 on page 52

PCLK2_Phase - adjusts the output phase of the

R/W

PCLK2 clock with respect to the timing output pins.

Phase is delayed in 700ps (nominal) increments as

shown in Table 3-6.

Reference: Section 3.7.1 on page 52

Divide_By_4 - set this bit HIGH to divide the output R/W

PCLK2 by four.

NOTE: Setting this bit and bit 0 simultaneously HIGH

will hold the PCLK2 pin LOW.

Reference: Section 3.7.1 on page 52

Divide_By_2 - set this bit HIGH to divide the output R/W

PCLK2 by two.

NOTE: Setting this bit and bit 1 simultaneously HIGH

will hold the PCLK2 pin LOW.

Reference: Section 3.7.1 on page 52

Reserved. Set these bits to zero when writing to

2Eh.

PCLK3_Phase - adjusts the output phase of the

R/W

PCLK3/PCLK3 clock with respect to the timing

output pins. Phase is delayed in 700ps (nominal)

increments as shown in Table 3-6.

Reference: Section 3.7.1 on page 52

Divide_By_4 - set this bit HIGH to divide the output R/W

PCLK3/PCLK3 by four.

Setting this bit and bit 0 simultaneously HIGH will

give the full rate video clock on the PCLK3 / PCLK3

pins.

Reference: Section 3.7.1 on page 52

Divide_By_2 - set this bit HIGH to divide the output R/W

PCLK3/PCLK3 by two.

Setting this bit and bit 1 simultaneously HIGH will

give the full rate video clock on the PCLK3 / PCLK3

pins.

Reference: Section 3.7.1 on page 52

Reserved. Set these bits to zero when writing to

2Fh.

Set these bits to 11b to tristate the PCLK3 / PCLK3

R/W

pins.

Reference: Section 3.7.1 on page 52

Default

00b

GS4901B/GS4900B SD Clock and Timing Generator

with GENLOCK

Data Sheet

37703 - 4

December 2009

77 of 102

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