GS4901B_09 Datasheet, PDF (23/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

1.5 Output Timing Signals
Table 1-3 describes the output timing signals available to the user via pins
TIMING_OUT_1 to TIMING_OUT_8. The user may output any of the signals listed below
on each pin by programming the Output_Select registers beginning at address 43h of the
host interface.
Table 1-3: Output Timing Signals
Signal Name
H Sync
H Blanking
V Sync
Description
Default Output Pin
The H Sync signal has a leading edge at the start of the horizontal sync
pulse. Its width is determined by the selected video standard (see
Table 1-2).
In Genlock mode the leading edge of the output H Sync signal is
nominally simultaneous with the half amplitude point of the reference
HSYNC input. This timing may be offset using the Genlock Offset registers
beginning at address 1Bh of the host interface (see Section 3.2.1.1 on
page 36).
By default, after system reset, the polarity of the H Sync signal output will
be active LOW. The polarity may be selected as active HIGH by
programming the Polarity register at address 56h of the host interface
(see Section 3.10.3 on page 67).
The H Blanking signal is used to indicate the portion of the video line not
containing active video data.
The H Blanking signal will be LOW (default polarity) for the portion of the
video line containing valid video samples. The signal will be LOW at the
first valid pixel of the line, and HIGH after the last valid pixel of the line.
The H Blanking signal remains HIGH throughout the horizontal blanking
period.
The width of this signal will be determined by the selected video standard
(see Table 1-2).
When in Genlock mode, the output H Blanking signal will be phase locked
to the reference HSYNC input. This timing may be offset using the
Genlock Offset registers beginning at address 1Bh of the host interface
(see Section 3.2.1.1 on page 36).
The default polarity of this signal may be inverted by programming the
Polarity register at address 56h of the host interface (see Section 3.10.3 on
page 67).
The V Sync timing signal has a leading edge at the start of the vertical sync
pulse. Its width is determined by the selected video standard (see
Table 1-2).
The leading edge of V Sync is nominally simultaneous with the leading
edge of the first broad pulse.
When in Genlock mode, the output V Sync signal will be phase locked to
the reference VSYNC input. This timing may be offset using the Genlock
Offset registers beginning at address 1Bh of the host interface (see
Section 3.2.1.1 on page 36).
By default, after system reset, the polarity of the V Sync signal output will
be active LOW. The polarity may be selected as active HIGH by
programming the Polarity register at address 56h of the host interface
(see Section 3.10.3 on page 67).
TIMING_OUT_1
TIMING_OUT_2
TIMING_OUT_3
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
23 of 102