GS4901B_09 Datasheet, PDF (51/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

3.6.3 Locking to Digital Timing from a Deserializer
As described in Section 3.4.1 on page 41, the GS4901B/GS4900B may be genlocked to
either an analog reference, such as a Black & Burst signal, or to an SDI input via the
digital H, V, and F blanking signals normally produced by a deserializer. When locking
to an SDI input, the user should consider the possibility of a switch of the SDI signal
upstream from the system.
If the GS4901B/GS4900B is locked to the digital H, V, and F blanking signals produced
by a deserializer, and the SDI input to the deserializer is switched such that the phase of
the H input changes abruptly, the REF_LOST output will remain LOW and the
GS4901B/GS4900B will not crash lock to the new H phase. Instead, the clock and timing
outputs will very slowly drift towards the new phase. During this period of drift, the
LOCK_LOST output will be LOW, even though the device is not genlocked.
The user should clear the Run_Window bits [2:0] of register adress 24h to force the
device to crash lock should such a switch occur. This will cause the GS4901B/GS4900B
to crash lock whenever it sees a disturbance of the input H signal.
NOTE: Any action that causes an abrupt phase change of the H input to the
GS4901B/GS4900B such that REF_LOST is not triggered will cause the device to respond
in the manner described above.
In addition to the slow drifting behaviour outlined above, there may also be a random
phase difference between the input VSYNC and output V Sync signals occurring each
time a switch in the SDI stream causes an abrupt phase change of the H input to the
GS4901B/GS4900B. This will only occur when attempting to lock the 525-line SD output
standards to the "f/1.001" HD input reference standards. All line-based timing outputs
are affected.
The only way to ensure a constant phase difference between the input VSYNC signal
and the line-based timing outputs is to reset the line-based counters after such a switch
occurs. This is acheived by toggling bit 15 of register address 83h in the host interface.
The device will then delay all line-based output timing signals by ΔVsync lines relative
to the input VSYNC reference, as described in NOTE 3 of Section 3.2.1.1 on page 36.
3.7 Clock Synthesis
The clock synthesis circuit generates the video clocks based on the VID_STD[5:0] pins
and host register settings. In the GS4901B, the clock synthesis circuit also generates the
audio clock signals based on the ASR_SEL[2:0] pins and host register settings.
The generated video and audio clocks may be further divided and are presented to the
application layer via pins PCLK1-PCLK3 and ACLK1-ACLK3 respectively.
3.7.1 Video Clock Synthesis
The video clock generator is referenced to an internal crystal oscillator and is
responsible for generating the PCLK output signals.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
51 of 102