GS4901B_09 Datasheet, PDF (36/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

The encoding scheme for the Clock_Phase_Offset register (1Dh) is shown in Table 3-1.
The offset programmed will be in the positive direction. Note that the step size will
depend on the frequency of the output video clock.
Table 3-1: Clock_Phase_Offset [15:0] Encoding Scheme
VID_STD[5:0]
Setting
Output Video Clock
Frequency
Step Size
(Fraction
of a PCLK)
Maximum
Number of
Steps
Bits Required to
Set the Number
of Steps
Clock_Phase_Offset [15:0]
Settings
1
f_PCLK < 20MHz
1
--------
512
511
b₈b₇b₆b₅b₄b₃b₂b₁b b₈000001b₈b₇b₆b₅b₄b₃b₂b₁b₀
0
3-6
20MHz < f_PCLK < 40MHz
1
--------
256
255
b₇b₆b₅b₄b₃b₂b₁b₀
b₇000010b₇b₆b₅b₄0b₃b₂b₁b₀
7-10
40MHz < f_PCLK < 54MHz
1
--------
128
127
b₆b₅b₄b₃b₂b₁b₀
b₆000100b₆b₅b₄00b₃b₂b₁b₀
Note: Program Clock_Phase_Offset = 0000 0000 0000 0000b to achieve a zero clock phase offset.
The value programmed in the H_Offset register (1Bh) must not exceed the maximum
number of clock periods per line of the outgoing video standard. Similarly, the value
programmed in the V_Offset register (1Ch) must not exceed the maximum number of
lines per frame of the outgoing standard. Both horizontal and vertical offsets will be in
the positive direction. Negative offsets (advances) are achieved by programming a value
in the appropriate register equal to the maximum allowable offset minus the desired
advance.
NOTES:
1. The device will delay all output timing signals by 2 PCLKs relative to the input
HSYNC reference. This will occur even when the H_Offset register is not
programmed. The user may compensate for this delay by subtracting 2 PCLK cycles
from the desired horizontal offset before loading the value into the host interface.
2. For both sync and blanking-based input references, the device will advance all
line-based output timing signals by 1 line relative to the input VSYNC reference for
all output standards except VID_STD[5:0] = 4, 6, and 8. This will occur even when
the V_Offset register is not programmed. The user may compensate for this
advance by adding 1 line to the desired vertical offset before loading this value into
the register.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
36 of 102