GS4901B_09 Datasheet, PDF (30/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
V_DD = 1.8V, T_A = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units Notes
System
Reference Detection Time
–
Digital I/O
PCLK Output Frequency
–
PCLK Jitter
–
PCLK Duty Cycle
–
PCLK1 & PCLK2 Rise/Fall Times
–
15pF load
20% - 80%
–
–
–
PCLK3 Rise/Fall Time
–
20% - 80%
PCLK Outputs Relative Timing
–
Skew
ACLK Frequency
–
(GS4901B only)
ACLK Duty Cycle
–
(GS4901B only)
ACLK1-3 Rise/Fall Times
–
15pF load
20% - 80%
(GS4901B only)
–
–
–
ACLK Outputs Relative
–
Timing Skew
(GS4901B only)
from when the
–
2
4
frames
–
reference input is
first present
–
3.375
–
165
MHz
–
XTAL_VDD = 3.3V
–
350
–
ps
1, 2
–
40
–
60
%
–
IO_VDD = 1.8V
–
current drive = LOW
–
1.7
ns
–
IO_VDD = 3.3V
–
current drive = LOW
–
1.5
ns
–
IO_VDD = 1.8V
–
current drive = HIGH
–
1.1
ns
–
IO_VDD = 3.3V
–
current drive = HIGH
–
0.9
ns
–
100Ω differential
–
load
10pF to ground per
pin
–
850
ps
–
default PCLK phase
-3
–
delay of zero
3
ns
3
–
0.0097
–
49.152
MHz
–
–
40
–
60
%
4
IO_VDD = 1.8V
–
current drive = LOW
–
3.0
ns
–
IO_VDD = 3.3V
–
current drive = LOW
–
1.5
ns
–
IO_VDD = 1.8V
–
current drive = HIGH
–
2.5
ns
–
IO_VDD = 3.3V
–
current drive = HIGH
–
1.4
ns
–
–
-3
–
3
ns
3
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
30 of 102