GS4901B_09 Datasheet, PDF (60/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

and stop lines of the USER signal on the even fields will be V_Start - 1 and V_Stop - 1,
respectively.
For example, if VID_STD[5:0] = 3, the odd fields will have 263 lines and the even fields
will have 262 lines. A user-defined vertical pulse programmed to start on line 12 and
stop on line 17 will start on frame lines 12 and 274, and stop on frame lines 17 and 279.
The designated registers for programming each user signal are located in the host
interface beginning at address 57h. See Section 3.10.3 on page 67.
V_Start
V_Stop
V_Start
V_Stop
AND=0, OR=0, XOR=0 (default)
AND=1
V_Start
V_Stop
V_Start
V_Stop
AND=0, OR=1
AND=0, OR=0, XOR=1
Shading indicates when USER_x signal is active
Figure 3-9: USER Programmable Output Signal
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
60 of 102