GS4901B_09 Datasheet, PDF (78/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
RSVD
Audio_Control
(GS4901B only)
Address
2Fh - 30h
31h
31h
31h
31h
31h
31h
31h
31h
Bit
–
15-10
9-7
6
5
4-3
2
1
0
Description
R/W
Reserved.
–
Reserved. Set these bits to zero when writing to
–
31h.
AFS_Reset_Window - These bits may be used to
R/W
adjust the value by which the audio clock counters
are allowed to drift from the output AFS pulse.
The encoding scheme for this register is shown in
Table 3-9.
NOTE: The default setting of this register will
provide a reset window that is sufficient for most
standards. To maintain correct audio clock
frequencies for some VESA standards, the reset
window may have to be increased from its default
setting. In this case, set the value of this register to
1XX. See Table 3-9.
Reference: Section 3.7.2 on page 54
Reserved. Set this it to zero when writing to 31h.
R/W
Enable_384fs - set this bit HIGH to enable the 384fs R/W
and 192fs audio clock outputs. This must be set in
addition to registers 3Fh to 41h.
NOTE: If this bit is HIGH, then a 512fs audio clock
will have a 33% duty cycle when fs = 96kHz.
Reference: Section 3.7.2 on page 54
Reserved. Set these bits to zero when writing to
–
31h.
Host_ASR_SEL - set this bit HIGH to select the audio R/W
sample rate using register 32h instead of the
external ASR_SEL[2:0] pins.
The external ASR_SEL[2:0] pins will be ignored, but
should not be left floating.
Reference: Section 3.7.2 on page 54
AFS_F_Pulse - set this bit to 1 to stretch the AFS
R/W
pulse duration from 1 line to 1 field.
Reference: Section 3.8.2 on page 59
AFS_Reset_Disable - set this bit HIGH to disable the R/W
10FID input reference pin from resetting the output
AFS pulse. If this bit is set HIGH, the output AFS
pulse will free-run or may be reset using register
1Ah. The external 10FID pin should not be left
floating.
Reference: Section 3.8.2 on page 59
Default
–
–
010b
0
0
–
0
0
0
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
78 of 102