GS4901B_09 Datasheet, PDF (80/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
ACLK2_fs_Multiple
(GS4901B only)
ACLK3_fs_Multiple
(GS4901B only)
RSVD
Output_Select_1
Address
40h
40h
41h
41h
42h
43h
43h
43h
Bit
15-3
2-0
15-3
2-0
–
15-5
4
3-0
Description
R/W
Reserved. Set these bits to zero when writing to
–
40h.
The user may set this register to select the desired R/W
frequency of the audio clock on ACLK2 (a multiple
of the fundamental sampling rate, fs). The audio
clock frequency may be set as: 512fs, 384fs, 256fs,
192fs, 128fs, 64fs, fs, or z-bit. See Table 3-8 for more
details.
NOTE: To output a frequency of 348fs or 192fs, bit 5
of register 31h must also be set HIGH.
Reference: Section 3.7.2 on page 54
Reserved. Set these bits to zero when writing to
–
41h.
The user may set this register to select the desired R/W
frequency of the audio clock on ACLK3 (a multiple
of the fundamental sampling rate, fs). The audio
clock frequency may be set as: 512fs, 384fs, 256fs,
192fs, 128fs, 64fs, fs, or z-bit. See Table 3-8 for more
details.
NOTE: To output a frequency of 348fs or 192fs, bit 5
of register 31h must also be set HIGH.
Reference: Section 3.7.2 on page 54
Reserved.
–
Reserved. Set these bits to zero when writing to
–
43h.
Current_1 - selects the current drive capability of
R/W
the TIMING_OUT_1 pin. Set this bit HIGH for high
current drive. Otherwise, the current drive will be
low.
Reference: Section 3.8.4 on page 62
This register is used to select one of the 10
R/W
pre-programmed or 4 user programmed timing
signals available for output on the TIMING_OUT_1
pin. See Table 3-11 for more details.
Note: The default setting of this register is 0001b,
which corresponds to H Sync.
Reference: Section 3.8.4 on page 62
Default
–
0
–
0
–
–
0
0001b
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
80 of 102