GS4901B_09 Datasheet, PDF (16/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
51
Name
PCLK1
52
PCLK1&2_GND
53
PCLK1&2_VDD
54
PhS_VDD
55
PhS_GND
56
JTAG/HOST
57
SCLK_TCLK
Timing
Type Description
–
Output CLOCK SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Video clock output signal.
PCLK1 presents a video sample rate clock output to the application
layer.
By default, after system reset, the PCLK1 output pin will operate at
the fundamental frequency determined by the setting of the
VID_STD[5:0] pins. It is possible to define other non-standard
fundamental clock rates using the host interface.
It is also possible to select different division ratios for the PCLK1
output by programming designated registers in the host interface.
A clock output of the fundamental rate, fundamental rate ÷2, or
fundamental rate ÷4 may be selected.
By setting designated registers in the host interface, the current
drive capability of this pin may be set high or low. By default, the
current drive will be low.
The PCLK1 output will be held LOW when VID_STD[5:0] = 00h.
–
Power Ground connection for PCLK1&2 circuitry. Connect to GND.
Supply
–
Power Most positive power supply connection for PCLK1&2 circuitry.
Supply Connect to +1.8V DC.
–
Power Most positive power supply connection for the video clock phase
Supply shift internal block. Connect to +1.8V DC.
–
Power Ground connection for the video clock phase shift internal block.
Supply Connect to GND.
Non
Input
Synchronous
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI
are configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI are
configured as GSPI pins for normal host interface operation.
Non
Input
Synchronous
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
All JTAG / Host Interface address and data are shifted into/out of
the device synchronously with this clock.
Host Mode (JTAG/HOST = LOW):
SCLK_TCLK operates as the host interface serial data clock, SCLK.
JTAG Test Mode (JTAG/HOST = HIGH):
SCLK_TCLK operates as the JTAG test clock, TCLK.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
16 of 102