GS4901B_09 Datasheet, PDF (45/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

internal flywheel ensures the selected output clock and timing signals maintain their
previous phase and frequency and continue to operate without glitches.
The VSYNC and FSYNC signals are not monitored in Genlock mode; loss of signal on
these pins will not affect the operation of the device.
NOTE 1: If the input reference is removed and re-applied, all line-based timing outputs
will be inaccurate for up to one frame for all output standards.
NOTE 2: When locking the SD input reference standards 3, 5, 7, or 9 to the “f/1.001” HD
input reference standards, there may be a random phase difference between the input
VSYNC and output V Sync signals occuring each time the input reference is removed
and re-applied. This will affect all line-based timing outputs. The user may reset the
line-based counters after the reference is re-applied without disrupting the pixel or
audio clocks by toggling bit 15 of register address 83h in the host interface. This will
cause the input VSYNC and line-based timing output signals to take on their default
timing relationship, as described in Note 3 of Section 3.2.1.1 on page 36.
Re-acquisition of the Same Reference
Upon re-application of the reference signal, the device checks whether the reference
has drifted more than +/- 2us from its expected location by comparing the current
relative position of the H pulses with the previous position, over a 16-line interval. If the
reference returns with the H pulses in the expected location +/- 2us, the PLL will drift
lock and the clock generator will continue to operate without a glitch. The REF_LOST
and LOCK_LOST pins will be set back LOW.
If the reference returns with the H pulses outside the +/- 2us window, the device will
crash lock the output timing to the new input phase. The principles of crash lock and
drift lock are described in Section 3.6.1 on page 49.
NOTE: To resume proper genlock operation upon re-application of the reference signal,
the user must implement the following register manipulation every time the reference
is removed and re-applied:
1. Read the value contained in register address 24h
2. Clear the Run_Window bits [2:0] of register 24h
3. Re-write the value read in step 1 to register address 24h.
This procedure will force the device to lock to the reference as described above, but will
maintain the flywheeling capability of the GS4901B/GS4900B should a single missing H
pulse occur in the genlocked state.
To avoid the above procedure, the user may choose to clear the Run_Window bits [2:0]
of register address 24h upon power-up or reset. However, this will disable the
flywheeling feature of the device that allows it to maintain genlock through one missing
input H pulse.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
45 of 102