GS4901B_09 Datasheet, PDF (61/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

3.8.4 TIMING_OUT Pins
The horizontal, vertical, and frame based timing output signals for the selected video
format are available to the application layer via the TIMING_OUT_1 to TIMING_OUT_8
pins.
Programmable Crosspoint Switch
Each TIMING_OUT pin outputs a default signal as shown in Table 1-3. Alternatively, a
crosspoint switch may be programmed via the eight Output_Select registers of the host
interface, allowing the user to select which output signal is directed to each
TIMING_OUT pin (see Section 3.10.3 on page 67). Any signal may be sent to more than
one pin if desired.
Table 3-11 outlines the encoding scheme of the eight Output_Select registers, which
begin at address 43h of the host interface.
Table 3-11: Crosspoint Select
Output_Select_n Bit Settings
Output Signal
0000
High Impedance
0001
H Sync
0010
H Blanking
0011
V Sync
0100
V Blanking
0101
F Sync
0110
F Digital
0111
10FID
1000
DE
1001
Reserved
1010
AFS*
1011
USER_1
1100
USER_2
1101
USER_3
1110
USER_4
1111
Reserved
*AFS is only available on the GS4901B. The bit setting 1010b will be ignored by the GS4900B.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
61 of 102