GS4901B_09 Datasheet, PDF (88/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
H_Start_3
H_Stop_3
V_Start_3
V_Stop_3
Address
61h
62h
63h
63h
64h
64h
Bit
15-0
15-0
15
14-0
15
14-0
Description
R/W
The value programmed in this register indicates the R/W
pixel start point for the leading edge of the
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must
be less than the value programmed in H_Stop_3.
Reference: Section 3.8.3 on page 60
The value programmed in this register indicates the R/W
pixel end point for the trailing edge of the
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must
not exceed the maximum number of clock periods
per line of the outgoing standard.
Reference: Section 3.8.3 on page 60
Reserved. Set this bit to zero when writing to 63h. –
The value programmed in this register indicates the R/W
start line number of the leading edge of the
user-programmed V Sync signal USER3_V. For
interlaced output standards, this value corresponds
to the odd field line number.
NOTE: The value programmed in this register must
be less than the value programmed in V_Stop_3.
Reference: Section 3.8.3 on page 60
Reserved. Set this bit to zero when writing to 64h. –
The value programmed in this register indicates the R/W
end line number of the trailing edge of the
user-programmed V Sync signal USER3_V. For
interlaced output standards, this value corresponds
to the odd field line number.
NOTE: The value programmed in this register must
not exceed the maximum number of lines per field
of the outgoing standard.
Reference: Section 3.8.3 on page 60
Default
0
0
–
0
–
0
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
88 of 102