GS4901B_09 Datasheet, PDF(66/102 Page) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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GS4901B_09 Datasheet, PDF (66/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

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Table 3-12: GSPI Timing Parameters (Continued)

Parameter

Definition

Specification

Duty cycle tolerated by SCLK.

40% to 60%

Minimum input setup time.

1.5 ns

The minimum duration of time between the last SCLK

command word (or data word if the Auto-Increment

bit is HIGH) and the first SCLK of the data word (write

cycle).

The minimum duration of time between the last SCLK

command word (or data word if the Auto-Increment

bit is HIGH) and the first SCLK of the data word (read

cycle).

Minimum output hold time (15pF load).

37.1 ns

148.4 ns

1.5 ns

The minimum duration of time between the last SCLK

of the GSPI transaction and when CS can be set HIGH.

Minimum input hold time.

37.1 ns

1.5 ns

SCLK

SDIN

R/W RSV RSV AutoInc A11 A10 A9

SDOUT

R/W RSV RSV AutoInc A11 A10

Figure 3-14: GSPI Read Mode Timing

D15 D14 D13 D12 D11 D10 D9

SCLK

SDIN R/W RSV RSV AutoInc A11 A10

SDOUT R/W RSV RSV AutoInc A11

A10 A9

D15 D14 D13 D12 D11 D10 D9

D15 D14 D13 D12 D11 D10

Figure 3-15: GSPI Write Mode Timing

3.10.3 Configuration and Status Registers

Table 3-13 summarizes the GS4901B/GS4900B's internal status and configuration

registers.

All registers are available to the host via the GSPI and are all individually addressable.

GS4901B/GS4900B SD Clock and Timing Generator

with GENLOCK

Data Sheet

37703 - 4

December 2009

66 of 102

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