GS4901B_09 Datasheet, PDF (41/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

3.4.2 10FID
The 10FID input is a reset pin, which can be used to reset the divider for the 10FID output
signal. In the GS4901B, the 10FID input pin will also reset the divider for the AFS output
signal. This default setting may be modified using the Audio_Control register of the host
interface (see Section 3.10.3 on page 67).
The GS4901B will reset the phase of the audio clocks to the leading edge of the H Sync
output on line 1 of every output frame in which the 10FID input is HIGH.
If the input reference format does not include a 10 Field ID signal, the external 10FID
input pin should be held LOW.
The timing of the 10FID input signal is shown in Figure 3-5.
Total Line
10FID Input
Horizontal Sync Input
Line 1, Frame 1 every 'n' frames
Line 1 every n frames where:
n = 5 @ 29.97 fps, 30 fps
n = 10 @ 59.94 fps, 60 fps
Figure 3-5: 10FID Input Timing
3.4.3 Automatic Polarity Recognition
To accommodate any standards that employ the polarity of the H and V sync signals to
indicate the format of the display, the GS4901B/GS4900B will recognize H and V sync
polarity and automatically synchronize to the leading edge.
The polarities of the HSYNC and VSYNC signals are reported in bits 3 and 4 of the
Video_Status register. Additionally, bit 2 of this register reports the detection of either
analog or digital input timing. See Section 3.10.3 on page 67 for detailed register
descriptions.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
41 of 102