GS4901B_09 Datasheet, PDF (48/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

3.6.1 Adjustable Locking Time
The GS4901B/GS4900B offers two different locking mechanisms to allow the user to
control the PLL lock time and the integrity of the output signal during the locking
process. The locking process is said to take place after the application of the input
reference and before the LOCK_LOST signal is set LOW.
By default, the internal PLL will crash lock. This locking process will ensure a minimum
PLL locking time; however, crash lock will cause the phase of the output clock and
timing signals to jump during the locking process. The crash behaviour of the video PLL
is controlled by the Crash_Time bits of register address 24h.
Alternatively, the user may set bit 1 of register 16h HIGH to force the PLL to drift lock.
Drift lock will increase the locking time of the PLL, but will maintain the signal integrity
of the output clock and timing pulses during the locking process.
As discussed in Section 3.5.3 on page 45, the device will normally drift lock when the
reference is removed and subsequently re-applied during Genlock mode.
3.6.2 Adjustable Loop Bandwidth
The default loop bandwidth of the GS4901B/GS4900B's internal video PLL is 10Hz when
the output video standard is the same as the input reference format. For other
cross-locking combinations, the default loop bandwidth may be smaller than 1Hz or as
large as 30Hz.
The user may adjust the loop bandwidth of both the video and audio PLLs depending on
the input, output, and audio standards selected. Increasing the loop bandwidth will
result in a shorter PLL lock time, but will allow more frequency components of jitter to
be passed to the outputs. Decreasing the loop bandwidth will decrease the output jitter,
but will result in a longer PLL lock time.
3.6.2.1 Loop Bandwidth of the Video PLL
The capacitive component of the filter controlling the video loop bandwidth is
determined by the Video_Cap_Genlock register and the resistive component is
determined by the Video_Res_Genlock register. These two registers are located at
addresses 26h and 27h, respectively, of the host interface.
To determine the setting of Video_Res_Genlock and Video_Cap_Genlock, the following
equations must be solved:
Video_Res_G enlock = 47 + log₂(6 × BW × JITTERIN × H _Feedback_D ivide )
Video_Cap_G enlock≤ Video_Res_G enlock– 21
where:
BW = the desired video PLL loop bandwidth
JITTERIN = Jitter present on applied HSYNC reference signal, in seconds
H_Feedback_Divide = the numerator of the video PLL divide ratio
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
48 of 102