GS4901B_09 Datasheet, PDF (24/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 1-3: Output Timing Signals (Continued)
Signal Name
V Blanking
F Sync
F Digital
Description
Default Output Pin
The V Blanking signal is used to indicate the portion of the video
field/frame not containing active video lines.
The V Blanking signal will be LOW (default polarity) for the portion of the
field/frame containing valid video data, and will be HIGH throughout the
vertical blanking period.
The width of this signal will be determined by the selected video standard
(see Table 1-2).
When in Genlock mode, the output V Blanking signal will be phase locked
to the reference VSYNC input. This timing may be offset using the Genlock
Offset registers beginning at address 1Bh of the host interface (see
Section 3.2.1.1 on page 36).
The default polarity of this signal may be inverted by programming the
Polarity register at address 56h of the host interface (see Section 3.10.3 on
page 67).
NOTE: When VID_STD = 4, 6, or 8, the Vblanking output pulse width is 2
lines too long for field 1 and 1 line too short for field 2 when compared to
the digital timing defined in ITU-R BT.656 and ITU-R BT.799.
The F Sync signal is used to indicate field 1 and field 2 for interlaced video
formats.
The F Sync signal will be HIGH (default polarity) for the entire period of
field 1. It will be LOW for all lines in field 2 and for all lines in progressive
scan systems.
The width and timing of this signal will be determined by the V Sync
parameters of the selected video standard (see Table 1-2). The F Sync
signal always changes state on the leading edge of V Sync.
When in Genlock mode, the output F Sync signal will be phase locked to
the reference FSYNC input. This timing may be offset using the Genlock
Offset registers beginning at address 1Bh of the host interface (see
Section 3.2.1.1 on page 36).
The default polarity of this signal may be inverted by programming the
Polarity register at address 56h of the host interface (see Section 3.10.3 on
page 67).
F Digital is used in digital interlaced standards to indicate field 1 and field
2.
The F Digital changes state at the leading edge of every V Blanking pulse.
It will be LOW (default polarity) for the entire period of field 1 and for all
lines in progressive scan systems. It will be HIGH for all lines in field 2 .
The width and timing of this signal will be determined by the timing
parameters of the selected video standard (see Table 1-2).
When in Genlock mode, the output F Digital signal will be phase locked to
the reference FSYNC input. This timing may be offset using the Genlock
Offset registers beginning at address 1Bh of the host interface (see
Section 3.2.1.1 on page 36).
The default polarity of this signal may be inverted by programming the
Polarity register at address 56h of the host interface (see Section 3.10.3 on
page 67).
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GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
24 of 102