GS4901B_09 Datasheet, PDF (49/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

H_Feedback_Divide represents the numerator of the ratio of the output clock frequency
to the frequency of the H reference signal.
For example, to program a loop bandwidth of 25Hz given a 54MHz video clock and a
reference with a 27MHz video clock and 1716 clocks per line, the following steps are
necessary:
1. Calculate H_Feedback_Divide:
-H----_---F----e--e---d---b---a---c---k--_----D----i--v--i--d---e-×
H _Reference_D ivide
f_{--f-p--H-c--r-l-ke---of---i-un---t}
f_pclkout = 27MHz
∴-H----_---F----e---e--d---b---a---c---k---_---D----i--v--i--d---e-=
27 × ^{1---7----1---6-}=
1716
-----------
H _Reference_D ivide
27 1
f_Hrefin
=
---2---7-----MHz
1716
Therefore, H_Feedback_Divide = 1716.
2. Calculate the value for Video_Res_Genlock:
Video_Res_G enlock = 47 + log₂(6 × 25 × (3 × 10^–9) × 1716) = 37
3. Calculate the value for Video_Cap_Genlock:
Video_Cap_G enlock = 37 – 21 = 16
Therefore, program Video_Res_Genlock = 37 and Video_Cap_Genlock = 16.
NOTE: The value programmed in the Video_Res_Genlock register must be between 32
and 42. The value programmed in the Video_Cap_Genlock register must be greater than
10. These limits define the exact range of loop bandwidth adjustment available.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
49 of 102