GS4901B_09 Datasheet, PDF (54/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-7: Audio Sample Rate Select
ASR_SEL[2:0]
Sampling Frequency (kHz)
000
Audio Clock Generation Disabled
001
32
010
44.1
011
48
100
96
101
Slow 32*
110
Slow 44.1*
111
Slow 48*
*Slow 32, 44.1, and 48 are available only when the video standard selected is 23.98, 29.97, or
59.94 frame rate based. They refer to 32kHz, 44.1kHz, or 48kHz multiplied by 1000/1001 to
maintain the 1, 2, or 3 frame sequence normally associated with 24, 30, and 60 fps video.
When all three ASR_SEL[2:0] pins are set LOW, the audio clock outputs will be high
impedance. In this case, the application layer may continue to power the
AUD_PLL_VDD pin; however, to minimize noise and power consumption,
AUD_PLL_VDD may be grounded.
By default, after system reset, ACLK1 to ACLK3 will output clock signals at 256fs, 64fs,
and fs respectively. Different division ratios for each output pin may be selected by
programming the ACLK_fs_Multiple registers beginning at address 3Fh of the host
interface (see Section 3.10.3 on page 67). The encoding of this register is shown in
Table 3-8. Clock outputs of 512fs, 348fs, 256fs, 192fs, 128fs, 64fs, fs, and z bit are
selectable on a pin by pin basis. The z bit will go HIGH for one fs period every 192 fs
periods. Its phase is not defined by any timing event in the GS4901B, and so is arbitrary.
Table 3-8: Audio Clock Divider
ACLKn_fs_Multiple[3:0]
000
001
010
011
100
101
110
Audio Clock Frequency
fs
64fs
128fs
192fs*
256fs
384fs*
512fs**
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
54 of 102