GS4901B_09 Datasheet, PDF (72/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
10FID_AFS_Reset
H_Offset
Address
1Ah
1Ah
1Ah
1Ah
1Ah
1Bh
Bit
15-4
3
2
1
0
15-0
Description
R/W
Reserved. Set these bits to zero when writing to
–
1Ah.
AFS_Reset (GS4901B only) - set this bit HIGH to use R/W
Reset_Sync (bit 0 of register 1Ah) to reset the
output AFS pulse.
NOTE: This bit will remain LOW in the GS4900B. Set
this bit LOW when writing to address 1Ah of the
GS4900B.
Reference: Section 3.7.2.1 on page 56
10FID_Reset - set this bit HIGH to use Reset_Sync (bit R/W
0 of register 1Ah) to reset the output 10FID pulse.
NOTE: If a 10FID input signal is not provided to the
device, the user must generate a reset using this bit
to initiate the 10FID timing output. In this case, the
10FID input pin must be grounded.
Reference: Section 3.7.2.1 on page 56
Reserved. Set this bit to zero when writing to 1Ah. –
Reset_Sync - resets the pulses described in bits 2,
R/W
and 3 above.
The reset pulse is generated if this bit is pulsed
(LOW to HIGH to LOW) during the output frame
immediately prior to the frame the reset is to occur.
This reset will operate independently of any other
resets, for example from the reference input.
The output H signal may be delayed with respect to R/W
the input reference by the number of pixels
programmed in this register. (See Section 3.2.1.1 on
page 36).
The value programmed in this register should not
exceed the maximum number of clock periods per
line of the outgoing standard. Horizontal advances
may be achieved by programming a value equal to
the maximum allowable offset minus the desired
advance.
NOTE: This register is internally read by the device
once per field. At that time any new value
programmed is sent to the internal offset circuitry.
Reference: Section 3.2.1.1 on page 36
Default
–
0
0
–
0
0
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
72 of 102