GS4901B_09 Datasheet, PDF (12/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
28, 29, 30
Name
ACLK1
ACLK2
ACLK3
(GS4901B only)
32, 33, 34
NC
(GS4900B only)
ASR_SEL[2:0]
(GS4901B only)
ANALOG_GND
(GS4900B only)
35
TIMING_OUT_1
Timing
Type Description
–
Output CLOCK SIGNAL OUTPUTS
Signal levels are LVCMOS/LVTTL compatible.
Audio output clock signals.
ACLK1, ACLK2, and ACLK3 present audio sample rate clock outputs
to the application layer.
By default, after system reset, the audio clock output pins of the
device provide clock signals as follows:
ACLK1 = 256fs
ACLK2 = 64fs
ACLK3 = fs, where fs is the fundamental sampling frequency.
The fundamental sampling frequency is selected using
ASR_SEL[2:0]. Additional sampling frequencies may be programmed
in the host interface.
It is also possible to select different division ratios for each of the
audio clock outputs by programming designated registers in the
host interface. Clock outputs of 512fs, 384fs, 256fs, 192fs, 128fs,
64fs, fs and z bit are selectable on a pin-by-pin basis.
NOTE: ACLK1-3 will have a 50% duty cycle, unless fs is selected as
96kHz and the host interface is configured such that one of the
three ACLK pins is set to output a clock signal at 192fs or 384fs. If
this is the case, then a 512fs clock will have a 33% duty cycle.
These signals will be high impedance when ASR_SEL[2:0] = 000b.
–
–
Do not connect.
Non
Input
Synchronous
CONTROL SIGNAL INPUTS
Signal levels are LVCMOS/LVTTL compatible.
Audio Sample Rate Select.
Used to select the fundamental sampling frequency, fs, of the audio
clock outputs. See Table 3-7.
When ASR_SEL[2:0] = 000b, audio clock generation will be disabled
and the ACLK1 to ACLK3 pins will be high impedance. In this case,
AUD_PLL_VDD (pin 14) may be connected to GND to minimize noise
and power consumption.
–
Power Ground connection for the analog input block. Connect to GND.
Supply
Synchronous
with PCLK1
~ PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio
timing (GS4901B only); USER_1~4.
See Section 1.5 on page 23 for signal descriptions.
NOTE: Default output is H Sync.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current
drive will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
12 of 102