GS4901B_09 Datasheet, PDF (9/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

1.3 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
1
Name
LOCK_LOST
2
REF_LOST
3
VID_PLL_VDD
4
VID_PLL_GND
5
XTAL_VDD
6
X1
7
X2
8
XTAL_GND
Timing
Type Description
Non
Synchronous
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be HIGH if the output is not genlocked to the input.
The GS4901B/GS4900B monitors the output pixel/line counters, as
well as the internal lock status from the genlock block and asserts
LOCK_LOST HIGH if it is determined that the output is not
genlocked to the input. This pin will be LOW if the device
successfully genlocks the output clock and timing signals to the
input reference.
If LOCK_LOST is LOW, the reference timing generator outputs will
be phase locked to the detected reference signal, producing an
output in accordance with the video standard selected by the
VID_STD[5:0] pins.
Non
Synchronous
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be HIGH if:
• No input reference signal is applied to the device; or
• The input reference applied does not meet the
minimum/maximum timing requirements described in
Section 3.5.2 on page 44.
This pin will be LOW otherwise.
If the reference signal is removed when the device is in Genlock
mode, REF_LOST will go HIGH and the GS4901B/GS4900B will enter
Freeze mode (see Section 3.2.1.2 on page 39).
–
Power Most positive power supply connection for the video clock synthesis
Supply internal block. Connect to +1.8V DC.
–
Power Ground connection for the video clock synthesis internal block.
Supply Connect to GND.
–
Power Most positive power supply connection for the crystal buffer.
Supply Connect to either +1.8V DC or +3.3V DC.
NOTE: Connect to +3.3V for minimum output PCLK jitter.
Non
Input
Synchronous
ANALOG SIGNAL INPUT
Connect to a 27MHz crystal or a 27MHz external clock source. See
Figure 1-1.
Non
Synchronous
Output
ANALOG SIGNAL OUTPUT
Connect to a 27MHz crystal, or leave this pin open circuit if an
external clock source is applied to pin 6. See Figure 1-1.
–
Power Ground connection for the crystal buffer. Connect to GND.
Supply
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
9 of 102