GS4901B_09 Datasheet, PDF (62/102 Pages) Gennum Corporation – SD Clock and Timing Generator with GENLOCK

3.8.4.1 Selectable Current Drive and Polarity
The current-drive of each timing output pin is also selectable via the Output_Select
registers. The current drive of each TIMING_OUT pin is low by default. However, it may
be set high to accommodate certain applications.
Additionally, the Polarity register of the host interface may be programmed to select the
polarity of each timing output signal.
3.9 Extended Audio Mode for HD Demux using the Gennum Audio
Core
The GS4901B/GS4900B has been designed to interface with Gennum's FPGA Audio
Core in order to provide a 24.576MHz clock (512 * 48kHz) locked to the audio clock
contained in the embedded audio data packets of an HD-SDI stream. It is the
responsibility of the user to divide this clock by 4 to obtain the 6.144MHz required by the
core.
In HD Demux mode, the FPGA Audio Core will extract an audio clock from the
embedded audio data packets and present a 24kHz clock to the GS4901B/GS4900B via
the aclkdiv2a (for Group A) and aclkdiv2b (for Group B) outputs. The embedded clock
must be 48kHz.
The 24kHz reference signals for each audio group must be applied to the HSYNC input
pin of a GS4901B/GS4900B, while a divided version of this signal must be applied to the
VSYNC input pin. The divided signal must meet the requirements for VSYNC validity
given in Section 3.5.2 on page 44. It is recommended that the VSYNC signal be generated
by dividing the 24kHz reference applied to HSYNC by 512 to give 46.875Hz.
To enable the extended audio mode, the user must do the following:
1. Set VID_STD[5:0] = 4d.
2. Set the F_Lock_Mask and V_Lock_Mask bits [4:3] of register address 16h to 1.
3. Set the Ext_Audio_Mode register address 81h to 20C1h.
4. Toggle bit [6] of register address 16h.
In this mode, the GS4901B/GS4900B will produce a 24.576MHz clock on its PCLK output
pins that is locked to the 24kHz extracted audio clock reference applied to HSYNC. It
will not lock to any other reference frequency. The user may then divide this frequency
by 4 using the programmable dividers in the GS4901B/GS4900B.
GS4901B/GS4900B SD Clock and Timing Generator
with GENLOCK
Data Sheet
37703 - 4
December 2009
62 of 102